Method of generating an initializing signal during power-up...

Details Method of generating an initializing signal during power-up... Method of generating an initializing signal during power-up...

2002-07-01

2004-09-14

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S203000, C365S233100

Reexamination Certificate

active

06791892

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a method of generating an initializing signal capable of preventing unstable operations of inner circuits when a semiconductor memory device is powered on.
2. Description of the Related Art
Power-up is to apply external electric power to a semiconductor memory device for operating the same. A semiconductor memory device includes an initializing circuit in order to prevent inner circuits from being unstably operated during power-up. Here, the unstable operations of the inner circuits mean that whether data in a circuit is logic ‘high’ or logic ‘low’ is difficult to be determined in a power-up operation section because external electric power is not completely stabilized. The unstable operations of the inner circuits can be prevented by latching the inner circuits through an initializing signal that is temporarily logic ‘high’ but drops to logic ‘low’ during the power-up.
FIG. 1
is a view of an initializing circuit
100
capable of preventing unstable operations of inner circuits of a semiconductor memory device upon power-up. Referring to
FIG. 1
, the initializing circuit
100
includes a PMOS transistor MP
1
, a capacitor CAP, a resistor R
1
and inverters I
11
through I
13
. In the operation of the initializing circuit
100
, an initializing signal VCCHB output from the initializing circuit
100
becomes larger due to an increase in a voltage level when external electric power EVC from an outer source is applied to the initializing circuit
100
and the voltage level of the external electric power EVC is raised. If the voltage level of the external electric power EVC is above a predetermined level, the voltage of the initializing circuit
100
is adjusted so that a first node N
11
becomes a logic ‘high’ level. Once the first node N
11
is recognized as logic ‘high’, the initializing signal VCCHB is generated to be logic ‘low’ by the inverters I
11
through I
13
. Here, the initializing pulse signal VCCHB is used for preventing unstable operation of the inner circuits of a semiconductor memory device during power-up operation.
FIG. 2
shows an example of a method of initializing the inner circuits of a semiconductor memory device using an initializing signal. In the operation of the circuit shown in
FIG. 2
, an input signal IN is inactive during power-up, and therefore a first node N
21
is in an unstable state. At this time, when a logic ‘high’ initializing signal VCCHB is input, a PMOS transistor MP
2
is turned on by an inverter I
21
and the first node N
21
is latched to the logic ‘high’ level and stabilized. As a result, variations in an output signal OUT can be prevented. When the initializing signal VCCHB is transited to the logic ‘low’ level, the PMOS transistor MP
2
is turned off and the first node N
21
remains latched to the logic ‘high’ level. As described above, the initializing signal VCCHB sets each of the nodes of the inner circuit of a semiconductor memory device to a predetermined logic level upon power-up.
However, the initializing circuit
100
has problems in that it has a large layout area and consumes power while the semiconductor memory device operates, even after the initializing signal VCCHB is generated. Further, the current trend is to reduce the voltage of the external electric power EVC (to conserve power and increase speed), thus lessening a voltage level of the initializing signal VCCHB. This causes the initializing signal VCCHB to fail to fulfill the function of preventing unstable operation of the inner circuits.
In contrast, a method of generating an initializing signal according to the present invention can reduce the layout area and power consumption of an initializing circuit during power-up.
SUMMARY OF THE INVENTION
To solve the above problems, it is an objective of the present invention to provide a method of generating an initializing signal capable of reducing the layout area and power consumption of an initializing circuit during power-up.
Accordingly, to achieve the above objective, there is provided a method of generating an initializing signal according to the first embodiment of the present invention. The method includes the steps of: (a) receiving a precharge command for precharging the semiconductor memory device; (b) activating the initializing signal to a first level in response to the received precharge command; (c) receiving a refresh command for refreshing the semiconductor memory device after receipt of the precharge command; (d) receiving a mode set command for setting an operational mode of the semiconductor memory device after receipt of the refresh command; and (e) deactivating the initializing signal to a second level in response to the received mode set command.
To achieve the objective, there is provided a method for generating an initializing signal according to the second embodiment of the present invention. The method includes the steps of: (a) receiving a precharge command for precharging the semiconductor memory device; and (b) generating an automatic pulse as an initializing signal in response to the received precharge command.
To achieve the objective, there is provided a method for generating an initializing signal according to the third embodiment of the present-invention. The method includes the steps of: (a) receiving a mode set command for setting an operational mode of the semiconductor memory device; and (b) generating an automatic pulse as an initializing signal in response to the received mode set command.
To achieve the objective, there is provided a method for generating an initializing signal capable of preventing initial unstable operations of inner circuits installed in a semiconductor memory device which includes an initializing circuit for preventing the inner circuits from being initially unstably operated due to the application of external electric power, according to a fourth embodiment of the present invention. The method includes the steps of: (a) the initializing circuit generating a pre-initializing signal in response to the external electric power; (b) receiving a mode set command for setting an operational mode of the semiconductor memory device; and (c) generating an automatic pulse in response to the pre-initializing signal and the received mode set command. The method may further include step (d) of turning off the initializing circuit in response to the generated initializing signal.
To achieve the objective, there is provided a method of turning off an initializing circuit for generating an initializing signal capable for preventing inner circuits installed in a semiconductor memory device from being initially unstably operated due to application of external electric power, according to a fifth embodiment of the present invention. The method includes the steps of: (a) the initializing circuit generating an initializing signal in response to the external electric power; (b) receiving a precharge command or precharging the semiconductor memory device; and (c) turning off the initializing circuit in response to the precharge command.
To achieve the objective, there is provided a method of turning off an initializing circuit for generating an initializing signal capable of preventing inner circuits installed in a semiconductor memory device from being initially unstably operated due to application of external electric power, according to a sixth embodiment of the present invention. The method includes the steps of: (a) the initializing circuit generating an initializing signal in response to the outer source of electric power; (b) receiving a mode set command for setting an operational mode of the semiconductor memory device; and (c) turning off the initializing circuit in response to the mode set command.


REFERENCES:
patent: 5703475 (1997-12-01), Lee et al.
patent: 5822766 (1998-10-01), Purdham et al.
patent: 5982704 (1999-11-01), Kim
patent: 6081460 (2000-06-01), Lim et al.
patent: 6633804 (2003-10-01), Dix et al.

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