Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-09-13
2004-12-28
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S741000
Reexamination Certificate
active
06836867
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of and an apparatus for generating a pattern for testing a logic circuit, and more particularly to such a method and an apparatus which are capable of shortening a length of a test pattern generated by an automatic test pattern generation (ATPG) system used for a combinational circuit and an automatic test pattern generation system used for a sequential circuit.
2. Description of the Related Art
As a scale of an integrated circuit such as LSI has become larger recently, a cost for testing an integrated circuit becomes higher. One of factors on which a cost for testing an integrated circuit is dependent is the number of patters for testing an integrated circuit. Less the number of test patterns is, shorter a period of time necessary for testing an integrated circuit is, ensuring that it is possible to shorten a period of time for using an expensive LSI tester, and hence, testing costs can be significantly reduced. Accordingly, there is a need of a method of reducing the number of test patterns.
In general, a test pattern generated by an automatic test pattern generation (ATPG) system used for a sequential circuit is different from a test pattern generated by an automatic test pattern generation system used for a combinational circuit, as follows.
The first difference is that a fault can be always detected by means of a signal test pattern in a combinational circuit, whereas a plurality of test patterns has to be used for testing a fault in many cases in a sequential circuit. Accordingly, the number of test patterns generated by an ATPG system used for a sequential circuit is likely to increase.
The second difference is as follows. In test patterns generated by an ATPG system used for a combination system, even if arrangement of respective test patterns were varied, a fault detecting rate obtained in an original arrangement of test patterns is not reduced. In contrast, in test patterns generated by an ATPG system used for a sequential system, if arrangement of respective test patterns were varied, there is often obtained a fault detecting rate which is lower than a fault detecting rate obtained in all original arrangement of test patterns. The reason is as follows. Since a sequential circuit includes a memory such as flip-flop (F/F) circuit, a value transmitted through an output terminal of the sequential circuit at a certain time is dependent on both a test pattern having been input into an input terminal of the sequential circuit and a logical value of a flip-flop circuit or internal condition of the sequential circuit at the certain time. Accordingly, if arrangement of respective test patterns were varied, the internal condition of the sequential circuit is also varied, resulting in that a fault which can be detected before the arrangement is varied can be no longer detected.
There is an increasing need for shortening a length of a test pattern generated by an ATPG system used for a sequential circuit, that is, a need for strengthening a function of test pattern compaction.
For instance, Japanese Unexamined Patent Publication No. 2000-329831 published on Nov. 30, 2000 has suggested an apparatus for compacting test patterns used for a combinational circuit in an ATPG system (hereinafter, the Publication is referred to as first prior art).
Though the first prior art is explained later, it should be noted that the applicant does not admit that the first prior art constitutes statutory prior art to the present invention. The first prior art is referred to herein merely for the purpose of better understanding of the present invention.
Japanese Unexamined Patent Publication No. 5-341011 has suggested a method of generating a test pattern (hereinafter, the Publication is referred to as second prior art).
The article identified below provides explanation about test pattern compaction in a logic circuit: B. Ayari and B. Kaminska, “A New Dynamic Test Vector Compaction for Automatic Test Pattern Generation”, IEEE Trans. Computer-Aided Design, Vol. 13, No. 3, Mar. 1994, pp. 353-358 (hereinafter, the article is referred to as the article A).
As introduced in the second chapter “Previous Work” in the article A, test pattern compaction is grouped into static compaction and dynamic compaction. In the static compaction, all test patterns which can detect faults are generated before test pattern compaction is carried out, and thereafter, test pattern compaction is carried out independently of generation of test patterns. In the dynamic compaction, automatic generation of test patterns which can detect faults and test pattern compaction for reducing the total number of test patterns are simultaneously carried out.
FIG. 1
is a flow chart showing steps to be carried out in the test pattern compaction in accordance with the first prior art. The test pattern compaction disclosed in the first prior art belongs to static compaction, and carries out the steps shown in
FIG. 1
to conduct test pattern compaction.
With reference to
FIG. 1
, first, circuit data and fault data are received, in the step S
2001
.
Then, there is generated test patterns to detect all faults, in the step S
2002
.
Then, arrangement of the thus generated test patterns is varied, in the step S
2003
.
Then, a logical value “1” or “0” is assigned to a primary input (PI) having a uncertain value (X value), among the test patterns, to thereby re-activate the test patterns, in the step S
2004
.
Then, fault simulation is conducted to the re-activated test patterns to identify the primary inputs which are not relevant to detection of all the faults, in all the test patterns, and assign uncertain values to the primary inputs, in the step S
2005
.
Then, test patterns which can be combined to one another are combined to one another among the test patterns to which the uncertain values were assigned, to thereby reduce the number of the test patterns, in the step S
2006
.
If the number of the test patterns is not adequately reduced, the steps S
2003
to S
2006
are repeated. If the number of the test patterns is adequately reduced, the compacted test patterns are output externally, in the step S
2007
. Thus, the test pattern compaction is completed.
FIG. 2
is a flow chart showing steps to be carried out in the test pattern compaction disclosed in the second prior art. The test pattern compaction disclosed in the second prior art belongs to dynamic compaction, and carries out steps shown in
FIG. 2
to generate test patterns.
Generation of test patterns starts in the step S
2101
, and then, there is made a fault list indicating faults to which test patterns are to be generated, in the step S
2102
.
Then, it is checked as to whether all faults are detected, in the step S
2103
.
If all the faults are detected (YES in the step S
2103
), generation of test patterns is finished in the step S
2114
.
If all the faults are not detected (NO in the step S
2103
), one of the faults is selected from the fault list at that time, in the step S
2104
. The thus selected fault is called a target fault.
Then, it is checked as to whether the test patterns having been generated so far have detected the target fault, in the step S
2106
.
If the target fault has been detected (YES in the step S
2105
), the step S
2103
is repeated.
If the target fault has not been detected (NO in the step S
2105
), a test pattern for detecting the target fault is generated, in the step S
2106
.
Then, it is checked as to whether the thus generated test pattern is single or not, in the step S
2107
.
If the generated test patter is plural (NO in the step S
2107
), it is checked as to whether a plurality of test patterns is selected among the test patterns, in the step S
2109
.
If a plurality of test patterns is selected (YES in the step S
2109
), fault simulation is conducted to one of the test patterns, in the step S
2110
.
Then, the number of faults having been detected in the test pattern to which the fault simulation was conducted is recorded, in the step S
2111
. The steps S
2110
and S
2
De'cady Albert
Kerveros James C.
McGinn & Gibb PLLC
NEC Electronics Corporation
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