Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-10-11
1998-11-24
Bowers, Charles
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438261, 438264, H01L 21336
Patent
active
058406077
ABSTRACT:
The present invention provides a method for forming a transistor having a stacked gate electrode structure with two gates; a lower floating gate and an upper control gate. The floating gate is formed of three polysilicon layers--undoped/doped/undoped polysilicon layers. A substrate is provided having a tunnel oxide layer 20. Then sequentially a first undoped, first doped, and second undoped polysilicon layers 22,24,26 are formed over the tunnel oxide layer thereby forming a lower floating gate layer 22, 24, 26. An intergate dielectric layer 28,30,32 is then formed over the second undoped polysilicon layer 26. Next, an upper control gate 36 and a cap oxide layer are formed over the intergate dielectric layer 28,30,32. The stacked two gate electrode structure is formed by patterning the above mentioned layers. Then spaced source and drain regions 44 are formed on opposite sides of the stacked gate structure thereby completing the transistor.
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Chuang Kuo-Sheng
Liao Siu-han
Yeh Jun-Ker
Yeou Long-Sheng
Ackerman Stephen B.
Bowers Charles
Chen Jack
Saile George O.
Stoffel William J.
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