Method of forming ultra-thin silicidation-stop extensions in...

Details Method of forming ultra-thin silicidation-stop extensions in... Method of forming ultra-thin silicidation-stop extensions in...

2006-01-24

2006-01-24

Nguyen, Thanh (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S592000, C438S595000, C438S289000, C438S299000, C438S301000, C438S303000

Reexamination Certificate

active

06989322

ABSTRACT:
Very low resistance, scaled in MOSFET devices are formed by employing thin silicidation-stop extension that act both as a silicidation “stop” barriers and as thin interface layers between source/drain silicide regions and channel region of the MOSFET. By acting as silicidation stops, the silicidation-stop extensions confine silicidation, and are not breached by source/drain silicide. This permits extremely thin, highly-doped silicidation-stop extensions to be formed between the silicide and the channel, providing an essentially ideal, low series resistance interface between the silicide and the channel.

REFERENCES:
patent: 2003/0136985 (2003-07-01), Murthy et al.
patent: 2004/0007724 (2004-01-01), Murthy et al.
patent: 2004/0132260 (2004-07-01), Lenoble
patent: 2004/0262683 (2004-12-01), Bohr et al.
patent: 2005/0087824 (2005-04-01), Cabral et al.

Affiliated with

Also associated with

Rating

Method of forming ultra-thin silicidation-stop extensions in... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming ultra-thin silicidation-stop extensions in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming ultra-thin silicidation-stop extensions in... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3591734