Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2002-11-19
2004-07-27
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S231000, C438S232000, C438S301000, C438S540000
Reexamination Certificate
active
06767809
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
NOT APPLICABLE
BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor manufacturing and, more particularly, to a method of forming ultra shallow junctions.
The escalating need for high densification and performance associated with large scale integrated semiconductor device requires design features of 0.25 microns and under, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.25 micron and under challenges the limitations of conventional semiconductor manufacturing techniques.
As design features continue to shrink below 0.25 micron, it is necessary to significantly reduce the depth of the source and drain regions below the surface of the semiconductor substrate of a typical MOS transistor, particularly the source/drain regions (i.e., the junction depth). The conventional method of forming such junctions involve ion implanting boron as p-type dopants for the source/drain or ion implanting arsenic or phosphorous as n-type dopants for the source/drain. The implantation is performed at very low energy levels to achieve a shallow junction depth. Because boron is an extremely light element, it is implanted at a very low energy. With a polysilicon gate width of 0.25 micron, the junction depth should be on the order of 800 Å. The ion energy for implanting boron is typically about 5 KeV. The resulting structure is then activation annealed, typically at about 800-1000° C. to cause activation of the boron dopant to form the source and drain regions.
Achievement of a small junction depth is problematic, especially for a p+ region formed using boron ions. It has been found that during dopant activation anneal, boron diffusion in the crystalline silicon layer is significantly large, so that the junction depth of the boron tends to be much deeper than planned. The problem becomes more critical as the design features shrink to 0.18 micron or 0.13 micron and below.
The problem of undefined dopant junction depth is believed to stem from various factors. For example, boron implantation is known to damage the monocrystalline silicon substrate generating interstitial atoms of silicon, i.e., silicon atoms that are displaced from the monocrystalline lattice to occupy spaces between silicon atoms in the monocrystalline lattice. During the high temperature activation anneal, boron diffuses into the monocrystalline silicon layer by attaching to the generated interstitial silicon atoms, causing an extremely rapid diffusion of boron into the monocrystalline silicon layer. Such a rapid boron diffusion causes the dopant profile and hence the junction depth to extend below the targeted maximum, despite the low initial implantation energy. This has been referred to as the transient enhanced diffusion (TED).
One approach to reduce or eliminate TED is to form an amorphous layer from the surface to a certain depth in the monocrystalline silicon by ion implanting germanium or silicon. Boron is then ion implanted into this amorphous silicon region. Subsequent annealing at high temperature avoids TED of boron due to the lack of interstitials. The amorphous silicon is recrystallized to monocrystalline silicon by solid phase epitaxy during activation annealing. The junction depth is controlled by selecting the appropriate ion implantation energy of boron.
To form the amorphous layer, a very high dose of Ge or Si has to be implanted. At such high doses, significant crystal damage is done to the silicon. It was found that the end-of-range damage remains upon crystallization of the surface amorphous region during activation annealing. The damage includes defects such as dislocations and stacking faults. The end-of-range defects in a subsequently formed depletion layer cause junction leakage, resulting in poor transistor performance. See U.S. Pat. Nos. 6,008,098 and 6,074,937.
BRIEF SUMMARY OF THE INVENTION
The present invention relates to a method of forming ultra shallow junctions having depths of 800 Å or less without requiring pre-amorphization implant thereby eliminating the end-of-range damage. In specific embodiments, the method involves implanting impurities such as boron ions into silicon and distributing the silicon interstitials within the desired junction depth to which the boron ions attach. This is accomplished by varying the ion implantation energy for implanting the impurities and maintaining the same dose. The maximum ion energy level is chosen to achieve the desired junction depth, while the minimum ion energy level is selected to achieve a desired distribution of the dopant impurities over the junction depth (e.g., a lower minimum ion energy will shift the concentration to a region close to the surface). Varying the ion energy produces more uniform interstitials and damage to the silicon substrate, and avoids the concentration of damage at a fixed depth. The more uniform distribution of interstitials and damage allows a reduction of the activation annealing temperature to activate the dopant impurities and remove the damage to the substrate. The lower anneal temperature reduces the thermal budget which is desirable particularly for shrinking device dimensions.
In accordance with an aspect of the present invention, a method of fabricating a semiconductor device comprises providing a semiconductor substrate, and ion implanting dopant impurities over a time period into the semiconductor device by varying an ion energy of implanting the dopant impurities over the time period. The dopant impurities are activation annealed to form one or more doped regions extending below the surface of the semiconductor substrate.
In some embodiments, the ion energy is varied continuously over the time period. The ion energy may be varied between a minimum energy level and a maximum energy level. The maximum energy level is selected to achieve a depth of the doped region which is smaller than a preset maximum depth. The minimum energy level is selected to achieve a desired distribution of the dopant impurities over a depth of the doped region. The ion energy may be varied cyclically during the time period. The ion energy may be varied in a stepwise manner over the time period. The dopant impurities may include boron ions. The activation annealing may be performed at a temperature of less than about 1000° C.
In accordance with another aspect of the invention, a method of fabricating a semiconductor device comprises providing a silicon substrate having a gate electrode and a gate oxide layer disposed thereon. Dopant impurities are ion implanted over a time period in the semiconductor device by varying an ion energy of implanting the dopant impurities over the time period. The method further includes activation annealing the dopant impurities to form doped source/drain regions extending below the surface of the silicon substrate on opposite sides of the gate electrode and gate oxide layer disposed thereon.
In accordance with another aspect of the present invention, a method of fabricating a semiconductor device comprises providing an ion implanter and providing a semiconductor substrate. Dopant impurities are ion implanted over a time period into the semiconductor device by varying an ion energy of the ion implanter and maintaining a direction of an ion beam of the ion implanter toward the semiconductor substrate to implant the dopant impurities over the time period. The method further includes activation annealing the dopant impurities to form one or more doped regions extending below the surface of the semiconductor substrate.
In some embodiments, the ion implanter includes an ion mass analyzer magnet current which is adjusted to maintain the purity and direction of the ion beam of the ion implanter toward the semiconductor substrate to implant the dopant impurities over the time period. In some other embodiments, the ion implanter includes a final energy magnet current which is adjusted to maintain the direction of the ion beam of the ion implanter tow
Picardat Kevin M.
SilTerra Malayisa Sdn. Bhd.
Townsend and Townsend / and Crew LLP
LandOfFree
Method of forming ultra shallow junctions does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming ultra shallow junctions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming ultra shallow junctions will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3190251