Method of forming trench MOS device and termination structure

Details Method of forming trench MOS device and termination structure Method of forming trench MOS device and termination structure

2000-09-22

2001-10-30

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S430000, C438S529000, C257S496000

Reexamination Certificate

active

06309929

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor process, specifically, to a novel termination structure for trench MOS devices so as to prevent leakage current.
BACKGROUND OF THE INVENTION
Doubled diffused metal-oxide-semiconductor field effect transistor (DMOSFET), insulated gate bipolar transistor (IGBT), and Schottky diode are important power devices and use extensively as output rectifiers in switching-mode power supplies and in other high-speed power switching applications. For example, the applications include motor drives, switching of communication device, industry automation and electronic automation. The power devices are usually required carrying large forward current, high reverse-biased blocking voltage, such as above 30 volt, and minimizing the reverse-biased leakage current. There are several reports that trench DMOS, trench IGBT and trench Schottky diode are superior to those of with planar structure.
For power transistors are concerned, apart from the device in the active region for carrying large current, there is still required a termination structure design in the periphery of the active region usually at an end of a die so as to prevent voltage breakdown phenomena from premature. Conventional termination structures include local oxidation of silicon (LOCOS), field plate, guard ring, or the combination thereof. The LOCOS is generally known to have bird beak characteristic. In the bird beak, electric field crowding phenomena is readily to occur, which is due to high impact ionization rate. As a result, leakage current is increased and electrical properties of the active region are deteriorated.
For example, please refer to
FIG. 1
, a semiconductor substrate with trench MOS structure for Schottky diodes, and a trench termination structure formed therein. The substrate is a heavily doped n+ substrate
10
and an epitaxial layer
20
formed thereon. A plurality of trench MOS
15
formed in the epitaxial layer
20
. The trench MOS devices including epitaxial layer
20
/gate oxide layer
25
/polysilicon layer
30
are formed in the active region
5
. The boundary of the active region
5
to the edge of the die is a LOCOS region of about 6000 Å in thick formed by conventional method.
For the purpose of lessening the electric field crowding issue, a p+-doping region
50
beneath LOCOS region is formed through ion implantation. The p+-doping region
50
is as a guard ring for reverse-biased blocking voltage enhancement. The anode (a metal layer)
55
is formed on the active region
5
and extends over p+ doping region
50
of LOCOS region. The object is to make the bending region of the depletion boundary far away from the active region
5
. Although guard ring
50
can alleviate the electrical field crowding and relax the bending magnitude occurred near the active region, the adjacent region between p+ region
50
and beneath the bottom of the trench MOS device, as arrow indicated denoted by
60
, is not a smooth curve. It will increase the leakage current and decrease the reverse-biased blocking capability. A similar situation occurred for field plate combines with guard ring. Furthermore, aforementioned prior art demanded more photo masks (at least four) to fabricate, and the processes are rather complicated. Still high cost for forming such structure is another inferior.
As forgoing several conventional termination structures can not solve the problems thoroughly. An object of the present invention thus proposes a novel termination structure. The new termination structure made the bending region of the depletion region far away from the active region, and depletion boundary is flatter than forgoing prior art. The manufacturing method provided by the present invention is even simpler than those prior arts. Since the termination structure and trench are formed simultaneously, it requires only three photo masks, low complicated processes and low cost.
SUMMARY OF THE INVENTION
The present invention discloses a method for fabricating trench MOS devices and termination structure simultaneously. The MOS devices can be Schottky diode, DMOS or IGBT, depending on the semiconductor substrate prepared, and are, respectively, illustrated in the first preferred embodiment, second preferred embodiment and third preferred embodiment. The method of the first preferred embodiment comprises following steps: firstly, forming a plurality of first trenches for forming the trench MOS devices in an active region, and a second trench for forming the termination structure. Thereafter, a thermal oxidation process proceeds to form a gate oxide on all areas. Then, the first trenches and the second trench are refilled with a first conductive material. An etching back process is carried out to remove excess first conductive material so as to form spacer on the second trench and to fill the first trenches only. Next, the gate oxide layer is removed. Thereafter, a termination structure oxide layer is formed through deposition, lithographic and etching processes. After backside unnecessary layers removal, a sputtering metal layers deposition, lithographic process and etching step are successively performed to form first electrode and second electrode on both side of semiconductor substrate.
For the second and third preferred embodiment, an extra thermal oxidation and an etching step are required to form inter-conductive oxide layer before termination structure oxide layer is deposited. So the first conductive layer is isolated from the second conductive layer by the inter-conductive oxide layer.


REFERENCES:
patent: 5888881 (1999-03-01), Jeng et al.
patent: 5949124 (1999-09-01), Hadizad et al.
patent: 6107662 (2000-08-01), Kim
patent: 6170815 (2001-01-01), Gil
patent: 6180441 (2001-01-01), Yue et al.
patent: 6184106 (2001-02-01), Chung
patent: 001096574A2 (2001-02-01), None

Affiliated with

Also associated with

Rating

Method of forming trench MOS device and termination structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming trench MOS device and termination structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming trench MOS device and termination structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2597821