Method of forming trench isolation regions

Details Method of forming trench isolation regions Method of forming trench isolation regions

2000-08-11

2002-01-01

Hiteshew, Felisa (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S700000, C438S706000, C438S745000

Reexamination Certificate

active

06335287

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming trench isolation regions in a semiconductor substrate.
2. Description of the Related Art
As the degree of integration of semiconductor devices increases, research has become more active in the fabrication of shallow trench isolation (STI) regions which exhibit excellent isolation characteristics even though they are smaller than more conventional local oxidation of silicon (LOCOS) regions. Generally, STI regions are fabricated by forming a trench in an isolation region of a semiconductor substrate, filling the trench with an insulating material, and planarizing the resultant surface by chemical mechanical polishing (CMP).
According to current planarizing processes employing CMP, complete planarization is not achieved due to a step difference in an insulating material layer extending between an active region where patterns are highly integrated (such as a cell array region or a peripheral circuit region) and a field region where few patterns exist. This step difference results from a difference in pattern densities between the two regions. Also, “dishing” occurs in wide isolation regions due to a bending characteristic of the pad of the CMP equipment. (Herein, “dishing” refers to an inward sloping of the material to form a shallow dish-like configuration.) The result is a final product having step differences which are not uniform over the entire wafer.
Excess polishing (i.e., over-polishing) is performed by CMP in an attempt to planarize the entire wafer, namely, to prevent the occurrence of the step difference between the finally formed isolation layer and the semiconductor substrate of the active region. At this time, the step difference between the isolation layer and the semiconductor substrate in the region where the patterns are integrated is different than the step difference between the isolation layer and the semiconductor substrate in the region where the patterns are not integrated. This results from the characteristic of the CMP process where the amount of etching varies according to the pattern density. The variation of the step difference remains after the isolation layer is formed and after all processes of forming a gate oxide layer (for example, a cleaning process) are performed, thus lessening the planarization of the entire surface of the wafer and causing a phenomenon where the electrical performance of the semiconductor device is not uniform over the entire wafer.
FIGS. 1 through 5
are sectional views for sequentially describing the processes of a general method for forming trench isolation regions.
Referring to
FIG. 1
, a CMP stopping layer (which forms CMP stopping patterns
12
) is formed on a semiconductor substrate
10
. The CMP stopping layer is then patterned to form CMP stopping patterns
12
which define windows therebetween for exposing the respective isolation regions. The semiconductor substrate
10
is then etched to a predetermined depth using the stopping patterns
12
as a mask. In this way, a wide trench
14
a
and narrow trenches
14
b
are formed in a field region A and a pattern region B, respectively. An insulating material layer
16
a
is then formed by depositing an insulating material of a suitable thickness to completely fill the trenches
14
a
and
14
b
and to cover the CMP stopping patterns
12
.
FIGS. 2 through 4
are sectional views for illustrating the manner in which the thicknesses of the insulating material layer and the CMP stopping patterns
12
change as the CMP process proceeds.
FIG. 2
shows the etched configuration of an insulating material layer
16
b
before the CMP stopping patterns
12
are completely exposed by the CMP process.
FIG. 3
shows the etched configurations of an insulating material layer
16
c
and the CMP stopping patterns
12
when the CMP stopping patterns
12
are completely exposed by the CMP process.
FIG. 4
shows the etched configurations of an insulating material layer
16
d
and the CMP stopping patterns
12
when the CMP stopping patterns
12
are excessively etched by the CMP process.
Referring again to
FIG. 2
, the insulating material layer
16
b
stacked on the CMP stopping patterns
12
around the wide trench
14
a
(of the region A) is not completely removed, and the insulating material layer
16
b
stacked on the CMP stopping patterns
12
around the narrow trenches
14
b
(of the region B) begins to expose the CMP stopping patterns
12
. At this time, the CMP process is not affected by the density of the CMP stopping patterns
12
, and instead the CMP process is affected only by the step difference of the initially coated insulating material layer (
16
a
of FIG.
1
).
Referring to
FIG. 3
, since the insulating material layer stacked on the CMP stopping patterns
12
are completely removed from the regions A and B, namely, since the CMP process is further performed until the insulating material layer (
16
b
of
FIG. 2
) stacked on the CMP stopping patterns
12
around the wide trench
14
a
(of the region A) is completely removed, the CMP stopping patterns
12
around the wide trench is completely exposed and the CMP stopping patterns
12
around the narrow trenches are etched by a predetermined thickness. Accordingly, the heights of the CMP stopping patterns
12
around the narrow trenches are reduced.
At this time, the height of the CMP stopping patterns
12
(marked “C”) adjacent to the wide trench
14
a
is reduced to the heights of the CMP stopping patterns
12
around the narrow trenches, and the amount of etching of the CMP stopping patterns
12
is larger toward the wide trench
14
a
in the pattern region B. This is because the CMP stopping patterns
12
formed around the wide trench
14
a
are etched more than the CMP stopping patterns
12
formed in other regions due to a dishing phenomenon which occurs in the wide trench
14
a
formed in the field region A resulting from the CMP process being characteristically affected by the density of the pattern.
The CMP stopping patterns
12
are formed of a material which is etched less by the CMP process than a material which forms the insulating material layer (
16
c
of FIG.
3
). During the CMP process, the region (the pattern region B) where the CMP stopping patterns are integrated is etched less than the region (the field region A) where the CMP stopping patterns are not integrated. Namely, the insulating material layer filled in the narrow trenches
14
b
is protected by the CMP stopping patterns
12
therearound. On the other hand, the insulating material layer filled in the wide trench
14
a
is not as protected by the CMP stopping patterns
12
therearound, and therefore the insulating material layer which fills the wide trench
14
a
is etched more quickly.
The CMP process, which is initially affected only by the density of the pattern, becomes affected by the bending characteristic of the pad as well as the density of the pattern as the CMP process proceeds further. Accordingly, the difference in the amount of etching of the insulating material layers between the two regions A and B becomes larger. As a result, the dishing phenomenon occurs resulting in a more severe bending of the surface of the insulating material layer
16
d
filled in the wide trench
14
a
. Further, the thicknesses of the CMP stopping patterns
12
are not uniform over the entire wafer since the CMP stopping pattern around the wide trench
14
a
is etched more than the CMP stopping patterns of other regions.
FIG. 4
is a sectional view showing the case where the CMP process is further performed in an attempt to planarize the finally formed isolation layer (the isolation layer before the formation of a gate oxide layer) and the semiconductor substrate
10
. As can be seen, the dishing phenomenon and the phenomenon where the thicknesses of the CMP stopping patterns
12
are not uniform over the entire wafer become more serious. The height T
1
of the CMP stoppin

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