Method of forming trench gate FETs with reduced gate to...

Details Method of forming trench gate FETs with reduced gate to... Method of forming trench gate FETs with reduced gate to...

2008-03-20

2009-02-03

Tran, Thien F (Department: 2895)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S270000, C438S271000

Reexamination Certificate

active

07485532

ABSTRACT:
A method for forming a FET includes the following steps. Trenches are formed in a semiconductor region of a first conductivity type. A well region of a second conductivity type is formed in the semiconductor region. Source regions of the first conductivity type are formed in the well region such that channel regions defined by a spacing between the source regions and a bottom surface of the well region are formed in the well region along opposing sidewalls of the trenches. A gate dielectric layer having a non-uniform thickness is formed along the opposing sidewalls of the trenches such that a variation in thickness of the gate dielectric layer along at least a lower portion of the channel regions is: (i) substantially linear, and (ii) inversely dependent on a variation in doping concentration in the lower portion of the channel regions. A gate electrode is formed in each trench.

REFERENCES:
patent: 5576245 (1996-11-01), Cogan et al.
patent: 5637898 (1997-06-01), Baliga
patent: 6365462 (2002-04-01), Baliga
patent: 6437386 (2002-08-01), Hurst et al.
patent: 6809375 (2004-10-01), Takemori et al.
patent: 7091573 (2006-08-01), Hirler et al.
patent: 2005/0116267 (2005-06-01), Zundel et al.
Non-Final Office Action mailed May 4, 2007 in U.S. Appl. No. 11/116,106.
Notice of Allowance mailed Oct. 10, 2007 in U.S. Appl. No. 11/116,106.
Notice of Allowance mailed Mar. 18, 2008 in U.S. Appl. No. 11/116,106.

Affiliated with

Also associated with

Rating

Method of forming trench gate FETs with reduced gate to... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming trench gate FETs with reduced gate to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming trench gate FETs with reduced gate to... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4085571