Method of forming transistor gate

Details Method of forming transistor gate Method of forming transistor gate

2000-11-30

2003-06-10

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S734000

Reexamination Certificate

active

06576515

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89119795, filed Sep. 26, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing semiconductor devices. More particularly, the present invention relates to a method of forming the gate of a stacked-gate non-volatile memory device such that effective area of the inter-gate dielectric layer (the dielectric layer between the control gate and the floating gate) inside the gate is increased.
2. Description of Related Art
All stacked-gate non-volatile memory such as erasable programmable read-only-memory (EPROM), electrically erasable programmable read-only-memory (EEPROM) and flash memory can hold data without the application of a voltage. Hence, stacked-gate non-volatile memory is ideal for storing frequently used and relatively permanent programs.
In general, the current-voltage characteristic of a stacked-gate non-volatile memory device can be inferred from the current-voltage characteristic and the capacitive coupling effects of a conventional metal-oxide-semiconductor device. Typically, the larger the capacitive coupling ratio of the non-volatile memory device, the lower will be the operating voltage required.
FIG. 1A
is a diagram showing the layout of a conventional stacked-gate non-volatile flash memory device after the floating gate is patterned.
FIG. 1B
is a diagram showing the gate layout of the device shown in FIG.
1
A.
FIG. 2
is a cross-sectional diagram along line II-II′ of FIG.
1
B. As shown in
FIGS. 1A and 1B
, the layout includes a gate region
58
and a non-gate region
60
.
FIG. 2
is in fact a cross-sectional diagram showing details of the gate region
58
and neighboring region according to FIG.
1
. As shown in
FIG. 2
, a gate structure is formed above a substrate. The substrate has a device structure therein. The device structure includes a semiconductor substrate
20
, a source terminal
22
and a drain terminal
23
. The gate structure includes a gate dielectric layer
24
, a conductive layer
26
, a conductive layer
50
, a dielectric layer
52
and a conductive layer
54
. The conductive layer
54
at least includes one layer. The gate dielectric layer
24
is a dielectric layer between the gate conductive layer
26
and the substrate
20
. The conductive layer
26
and the conductive layer
50
together constitute a floating gate. The dielectric layer
52
is an inter-gate dielectric layer. The conductive layer
54
is a control gate.
A conventional stacked-gate type non-volatile flash memory device has altogether four contact capacitors. They are the contact capacitor C
FG
between the floating gate (the conductive layer
26
and the conductive layer
50
) and the control gate (the conductive layer
54
), the contact capacitor C
B
between the floating gate (the conductive layer
26
and the conductive layer
50
) and the substrate (the semiconductor substrate
20
), the contact capacitor C
S
between the floating gate (the conductive layer
26
and the conductive layer
50
) and the source terminal
22
and the contact capacitor C
D
between the floating gate and the drain terminal
23
.
The capacitive coupling ratio can be represented by the following formula:
Capacitive
⁢
 
⁢
coupling
⁢
 
⁢
ratio
=
C
FG
C
FG
+
C
B
+
C
S
+
C
D
According to the above formula, when the capacitance of the contact capacitor C
FG
between the floating gate (the conductive layer
26
and the conductive layer
50
) and the control gate (the conductive layer
54
) increases, the capacitive coupling ratio also increases.
In general, the capacitive coupling ratio can be increased by increasing the effective area of the inter-gate dielectric layer, lowering the thickness of the inter-gate dielectric layer and increasing the dielectric constant k of the inter-gate dielectric layer.
However, the inter-gate dielectric layer must have sufficient thickness to prevent electrons trapped inside the floating gate (the conductive layer
26
and the conductive layer
50
) from entering into the control gate (the conductive layer
54
) and resulting in device failure. On the other hand, increasing the dielectric constant of the inter-gate dielectric layer involves the use of new material and equipment for processing the material. Hence, the process cannot be easily implemented. Ultimately, the only option for increasing the capacitive coupling ratio falls back to increasing the effective surface area of the inter-gate dielectric layer so that the capacitance of the contact capacitance C
FG
between the floating gate (the conductive layer
26
and the conductive layer
50
) and the control gate (the conductive layer
54
) is increased.
However, as shown in
FIG. 1A
,
1
B and
2
, the conductive layer
50
is of the stacked-type. Hence, the increase in effective surface area is quite limited. Furthermore, when the dielectric layer
52
and the conductive layer
54
are patterned, the conductive layer
54
in the non-gate region
60
, the dielectric layer
52
, the conductive layer
50
and the conductive layer
26
must be removed simultaneously. Since the conductive layer
50
has a definite thickness, much thicker layer of the dielectric layer
52
needs to be removed by etching in the vertical direction than in the horizontal direction. Hence, some residues from the dielectric layer
52
are likely to remain.
In addition, signal storage in a dynamic random access memory is achieved through selectively charging and discharging of the capacitors on the surface of a semiconductor substrate. The execution of read/write operation is effected by moving electric charges into or away from a capacitor via a transfer field effect transistor connected to a bit line.
Capacitor is one of the principle components in a dynamic random access memory. Any reduction in capacitance accompanied by a reduction in memory cell area is likely to limit memory density. A reduction in memory cell capacitance will increase read-out difficulties and soft errors. Moreover, the use of low operating voltage may lead to large power consumption. An effective means of increasing capacitance is to increase the effective surface area of the dielectric layer between the upper and the lower electrode of a capacitor.
FIG. 3
is a cross-sectional view showing a conventional stack capacitor. As shown in
FIG. 3
, the stack capacitor includes a semiconductor substrate
80
having a device structure
82
therein. A dielectric layer
84
is above the semiconductor substrate
80
and the dielectric layer has a via opening
86
that exposes a portion of the device structure
82
. The stack capacitor also includes the lower electrode
88
of a conventional stack transistor. The lower electrode
88
fills the via opening
86
and covers a portion of the dielectric layer
84
around the via opening
86
. The lower electrode
88
has a stacked-type profile. Due to shape limitation, such a lower electrode
88
only has moderate surface area.
A cylindrical capacitor has a greater surface area but processing demands more masking operations, and hence increases production time and complexity.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a transistor gate structure and a method of forming the transistor gate capable of increasing effective surface area of the inter-gate dielectric layer inside a transistor gate and reducing etching thickness of the inter-gate dielectric layer in the vertical direction.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a transistor gate. First, a gate dielectric layer is formed over a substrate. The lower section of a floating gate is formed over the gate dielectric layer. A source/drain region is formed in the substrate, one on each side of the lower section of the floating gate. A first dielectric layer is formed over the substrate.

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