Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Polycrystalline semiconductor
Reexamination Certificate
1999-01-29
2002-08-06
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Polycrystalline semiconductor
C438S489000, C438S491000, C438S530000, C438S592000, C438S593000, C438S775000
Reexamination Certificate
active
06429101
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a process for producing a thermally stable non-monocrystalline semiconductor to monocrystalline electrical contact structure. The invention also relates to devices including such a thermally stable monocrystalline to non-monocrystalline electrical contact structure.
BACKGROUND OF THE INVENTION
Many semiconductor devices include a region of monocrystalline semiconductor adjacent a region of non-monocrystalline semiconductor. Non-monocrystalline semiconductor can include amorphous semiconductor as well as polycrystalline semiconductor. Often, after non-monocrystalline semiconductor is deposited on monocrystalline semiconductor, the structure that includes the monocrystalline semiconductor and non-monocrystalline semiconductor may still be subjected to further processing steps. Often, the further processing steps cause changes in the monocrystalline semiconductor, non-monocrystalline semiconductor as well as dopants and other materials in the semiconductors.
For example, further processing steps may subject the monocrystalline semiconductor and non-monocrystalline semiconductor to heat. Heat may cause the grain or crystal size of the non-monocrystalline semiconductor to change. Heat may also cause dopants in the monocrystalline semiconductor and non-monocrystalline semiconductor to be redistributed. Another effect of heat may be to shift the boundary between the monocrystalline semiconductor and the non-monocrystalline semiconductor.
The boundary shift may occur as because not only may non-monocrystalline semiconductor material undergo grain size change, but it may also regrow epitaxially into and/or onto monocrystalline semiconductor. Large grains of polycrystalline semiconductor material may grow preferentially and consume material in smaller grains. This process of crystal or grain size growth may be driven by free energy of the crystal boundaries. Polycrystalline semiconductor may have lower free energy when it includes larger grain sizes.
The larger grain sizes also result in a smaller area in the grain boundaries. If non-monocrystalline semiconductor, particularly polycrystalline semiconductor is in contact with monocrystalline semiconductor, the monocrystalline semiconductor may, in effect, act as a very large grain compared to the monocrystalline or non-monocrystalline semiconductor. As a result, during high temperature treatments, material from polycrystalline semiconductor, in particular, may undergo grain growth by realigning epitaxially into or onto the monocrystalline semiconductor matrix.
Such grain regrowth in polycrystalline silicon may begin at temperatures of about 900° C. The temperature may be slightly lower if the polycrystalline silicon is n-type or p-type doped. If the polycrystalline silicon is totally amorphized, then epitaxial regrowth may take place at temperatures in the range of about 500° C.
Changes in the semiconductor structure can lead to degradation of electrical contact characteristics and/or create defects that can propagate into the monocrystalline semiconductor material. Often, the structures that include monocrystalline semiconductor and an adjacent non-monocrystalline semiconductor are utilized as semiconductor contacts. One example of such a contact is a buried strap.
Such a buried strap may be utilized in, among other applications, 0.25 &mgr;m and smaller MINT DRAM memory cells. One memory cell utilizing such a buried strap and including a monocrystalline
on-monocrystalline interface experiences variable retention time problems. These problems may be caused by defects that propagate from epitaxially regrown regions of polycrystalline semiconductor into monocrystalline semiconductor.
In the “buried strap” structure in 0.25 &mgr;m and below trench DRAM's mentioned above, an interface exists between non-monocrystalline silicon and monocrystalline silicon. The buried strap is an abutted polycrystalline silicon to monocrystalline silicon connection fabricated to provide electrical continuity between a monocrystalline silicon diffusion layer and polycrystalline silicon filling inside of the storage trench of the device. Subsequent to depositing this connection there are several high temperature processing steps at temperatures in excess of about 900° C. during which it is possible for epitaxial regrowth to occur.
DRAM cells are very sensitive to the presence of crystal defects in the junctions that make up the storage node. For example, it has been observed that the 0.25 &mgr;m DRAM suffered from a tendency to form dislocations more than previous DRAM generations. It has been demonstrated that dislocations may be generated due to epitaxial growth of polycrystalline silicon in the trench onto the monocrystalline silicon of the substrate. It has also been observed that monocrystalline silicon material formed during epitaxial regrowth may contain many crystal defects. Some of these defects may be free to propagate into the monocrystalline semiconductor substrate region where they can produce undesirable leakage. It also may be possible that the epitaxial regrowth produces a flux of point defects which then coalesce to produce a dislocation under the influence of stress in the single crystal region. In any case, the solution to this problem is to suppress the epitaxial regrowth of the polycrystalline semiconductor into and/or onto monocrystalline semiconductor.
Of course, the buried strap structure discussed above is only one example of a structure that includes an interface between monocrystalline semiconductor and polycrystalline semiconductor where the above discussed problems may manifest themselves.
SUMMARY OF THE INVENTION
To provide a solution to the above-discussed and other problems, aspects of the present invention provide a method for forming a thermally stable ohmic contact structure including a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of dielectric material is formed between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor, thereby controlling grain growth of the polycrystalline semiconductor.
Other aspects of the present invention provide a method for forming a thermally stable structure including a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of electrically conducting material is provided between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor.
Additional aspects of the present invention provide a method for forming a thermally stable structure including a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of polycrystalline semiconductor material with a lattice mismatch with respect to the monocrystalline semiconductor is deposited between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor.
Further aspects of the present invention provide a method for forming a thermally stable structure including a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. The region of polycrystalline semiconductor is deposited on a surface of the region of monocrystalline semiconductor. At least one impurity is introduced into the polycrystalline semiconductor as it is being deposited.
Still further aspects of the present invention provide a method for forming a thermally stable structure including a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of amorphous semiconductor material is deposited adjacent the region of monocrystalline semiconductor material. The amorphous semiconductor is then crystallized to form the polycrystalline semiconductor.
Additional aspects of the present invention provide a method for forming a thermally stable structure including a region of monocrystalline semiconductor and a region of polycrystalli
Amos Ricky S.
Ballantine Arne W.
Bazan Gregory
Chen Bomy A.
Coolbaugh Douglas D.
Connolly Bove & Lodge & Hutz LLP
International Business Machines - Corporation
Nguyen Ha Tran
Sabo William D.
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