Method of forming TaC gate electrodes with crystal...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S199000, C438S231000, C257S365000, C257S369000, C257S388000, C257S407000, C257S412000, C257S627000, C257S628000

Reexamination Certificate

active

07632728

ABSTRACT:
A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.

REFERENCES:
patent: 5873955 (1999-02-01), Kirino et al.
patent: 6271573 (2001-08-01), Suguro
patent: 2006/0145201 (2006-07-01), Shiga
patent: 2006/0197157 (2006-09-01), Koyama et al.
patent: 2007/0048919 (2007-03-01), Adetutu et al.
patent: 2007/0145488 (2007-06-01), Koyama et al.
patent: WO 2004009515 (2004-01-01), None
Schaeffer, J. K. et al., “Challenges for the Integration of Metal Gate Electrodes,” IEEE, 2004 IEDM, pp. 287-290, (2004).

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