Method of forming T-shaped isolation layer, method of...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S300000, C438S301000, C438S427000, C438S682000

Reexamination Certificate

active

06383877

ABSTRACT:

BACKGROUND OF THE INVENTION
The present application claims priority under 35 U.S.C. §119 to Korean Patent Application Nos. 99-18268 and 99-43784, respectively filed on May 20, 1999 and Oct. 11, 1999.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having an isolation layer of improved structure, a method of forming the isolation layer, and a method of forming a source/drain region using the isolation layer.
2. Description of the Related Art
As the integration density of semiconductor devices increases, isolation techniques for electrically isolating adjacent transistors from each other become more important. A local oxidation of silicon (LOCOS) process is a typical isolation technique. However, the LOCOS process is known to be unsuitable for highly integrated semiconductor devices having a design rule less than or equal to 0.5 &mgr;m. Therefore, a trench isolation technique involving the formation of a trench in a predetermined region of a semiconductor substrate using a photolithography process and the formation of an isolation layer by filling the trench with an insulating material can be used.
The aspect ratio of trenches formed using conventional trench isolation techniques has recently been increased to be greater than or equal to 3, in order to keep up with the increasing integration density of semiconductor devices. As a result, trench isolation causes problems. Namely, when a trench having aspect ratio greater than or equal to 3 is filled with insulating material using an established deposition method such as a chemical vapor deposition (CVD) method, an overhang phenomenon occurs at the entrance to the trench. Accordingly, a void is formed in the trench. When a trench isolation layer is formed by performing a planarizing process such as a chemical mechanical polishing (CMP) process in a following step, the void formed in the trench may be opened. The opening of the void can reduce the reliability of the semiconductor device. To be specific, a process of forming a gate electrode may be performed after forming the trench isolation layer. At this time, a bridge occurs between adjacent gate electrodes since the opened void formed in the trench is filled with a conductive material such as conductive polysilicon during formation of the gate electrode.
Therefore, a method of filling the trench with a material such as undoped silicate glass (USG) having excellent gap-filling characteristics has recently been used. However, even with the use of special gap-filling materials, when the aspect ratio of the trench exceeds certain limits, it is not possible to prevent a void from occurring.
Also, when the aspect ratio of the trench increases, problems are caused during a wide-region planarizing process which must be performed in order to complete the formation of the isolation layer. In conventional trench isolation techniques, it is usual to planarize the entire surface of the semiconductor substrate after filling the trench that is formed by a photolithography process with insulating material. When the aspect ratio of the trench increases, a severe step difference is formed on the entire surface of the semiconductor substrate on which the insulating material is deposited. Therefore, it is not possible to obtain a desired degree of planarization even though the entire surface of the semiconductor substrate is wide-region planarized.
After the trench isolation layer is formed according to conventional technology, a semiconductor device such as an MOS transistor is formed on an active region defined by the isolation layer. Namely, a gate electrode is formed by interposing a gate oxide layer on the active region and source/drain regions are formed on both sides of the gate electrode. In the case of a semiconductor device having a design rule less than or equal to 0.2 &mgr;m, the source/drain region is formed to be thin in order to improve the operating characteristics of the semiconductor device. In addition, a silicide layer is formed by performing a salicide process on the gate electrode and the source/drain region in order to reduce the signal delay time of the semiconductor device. When the silicide layer is formed on the source/drain region by performing the salicide process, junction leakage current becomes greater at the boundary between the isolation layer and a junction region than if the salicide process had not been performed. In order to solve this problem, a method of forming the source/drain region as elevated above the semiconductor substrate and then performing the salicide process on the elevated source/drain region has recently been suggested. However, it is not possible to reduce the junction leakage current below the desired value even though the salicide process is performed after forming the elevated source/drain region.
The above problems of the conventional method of forming the trench isolation layer will now be described with reference to
FIGS. 1A through 2C
.
Referring to
FIG. 1A
, after forming a trench
12
in a predetermined portion of a semiconductor substrate
10
, the trench
12
is filled with a gap-filling dielectric layer
14
. For example, the trench
12
can be filled with a silicon oxide layer formed on the entire surface of the semiconductor substrate
10
using a CVD method. As mentioned before, when the aspect ratio of the trench
12
is greater than or equal to 3, an overhang phenomenon occurs at the entrance to the trench
12
as the deposition process proceeds. As a result, a void
16
is formed in the trench
12
.
Referring to
FIG. 1B
, a trench isolation layer
14
is formed by planarizing the entire surface of the semiconductor substrate
10
using, for example, a CMP method. The void formed in the trench isolation layer
14
is opened during the planarizing process. As a result, in a next step of forming a gate with a gate electrode material, the void is filled with the gate electrode material, so that a bridge is created between adjacent gate electrodes.
FIG. 2A
is a plan view showing a portion of the semiconductor substrate
10
after forming trench isolation layers A, gate electrodes B, and active regions C.
FIG. 2B
is a sectional view taken along the line X-X′ of FIG.
2
A. Referring to FIG.
2
A and
FIG. 2B
, the active regions C are defined by forming the trench isolation layers A in predetermined portions of the semiconductor substrate
10
. A void
16
having an upper portion that is opened is formed in the trench isolation layer A. The gate electrodes B under which the gate oxide layer is interposed are formed by sequentially forming the gate oxide layer (not shown) and the polysilicon layer on the semiconductor substrate
10
and performing a photolithography process. At this time, the void
16
having an upper portion that is opened is filled with the conductive material, for example, polysilicon
18
which forms the gate electrode B. Furthermore, the polysilicon inside the void
16
is not completely removed in the photolithography process used to pattern the gate electrodes. This results in the formation of the bridge I between the adjacent gate electrodes B.
Referring to
FIG. 2C
, which is a sectional view taken along the line Y-Y′ of
FIG. 2A
, the bridge I generated between the adjacent gate electrodes B is clearly visible. The void
16
having an upper portion that is opened and which is formed in the trench isolation layer A is filled with polysilicon
18
. Accordingly, the bridge I is formed between the adjacent gate electrodes B. This reduces the reliability of the semiconductor device.
The problems of the conventional method of forming the elevated salicide source/drain region will now be described with reference to
FIGS. 3 through 6
. Referring to
FIG. 3
, a trench isolation layer
20
is formed on the semiconductor substrate
10
. A gate electrode pattern G including a gate oxide layer
21
, a gate electrode
22
, and a side-wall spacer
23
is formed on an active region

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