Method of forming strained silicon on insulator substrate

Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – On insulating substrate or layer

Reexamination Certificate

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Reexamination Certificate

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06911379

ABSTRACT:
A method of forming a strained-silicon-on-insulator substrate is disclosed. A target wafer includes an insulator layer on a substrate. A donor wafer includes a bulk semiconductor substrate having a lattice constant different from a lattice constant of silicon and a strained silicon layer formed on the bulk semiconductor substrate. The top surface of the donor wafer is bonded to the top surface of the target wafer. The strained silicon layer is then separated from the donor wafer so that the strained silicon layer adheres to the target wafer. The bond between the strained silicon layer and the target wafer can then be strengthened.

REFERENCES:
patent: 4072974 (1978-02-01), Ipri
patent: 5013681 (1991-05-01), Godbey et al.
patent: 5024723 (1991-06-01), Goesele et al.
patent: 5213986 (1993-05-01), Pinker et al.
patent: 5374564 (1994-12-01), Bruel
patent: 5468657 (1995-11-01), Hsu
patent: 5633588 (1997-05-01), Hommei et al.
patent: 5659192 (1997-08-01), Sarma et al.
patent: 5663588 (1997-09-01), Suzuki et al.
patent: 5739574 (1998-04-01), Nakamura
patent: 5759898 (1998-06-01), Ek et al.
patent: 5769991 (1998-06-01), Miyazawa et al.
patent: 5792669 (1998-08-01), Baumann et al.
patent: 5863830 (1999-01-01), Bruel et al.
patent: 5882981 (1999-03-01), Rajgopal et al.
patent: 5882987 (1999-03-01), Srikrishnan
patent: 5904539 (1999-05-01), Hause et al.
patent: 6023082 (2000-02-01), McKee et al.
patent: 6143070 (2000-11-01), Bliss et al.
patent: 6159824 (2000-12-01), Henley et al.
patent: 6207005 (2001-03-01), Henley et al.
patent: 6252284 (2001-06-01), Muller et al.
patent: 6291321 (2001-09-01), Fitzgerald
patent: 6326285 (2001-12-01), Behfar et al.
patent: 6335231 (2002-01-01), Yamazaki et al.
patent: 6355541 (2002-03-01), Holland et al.
patent: 6358806 (2002-03-01), Puchner
patent: 6368938 (2002-04-01), Usenko
patent: 6407406 (2002-06-01), Tezuka
patent: 6410371 (2002-06-01), Yu et al.
patent: 6410938 (2002-06-01), Xiang
patent: 6429061 (2002-08-01), Rim
patent: 6455398 (2002-09-01), Fonstad, Jr. et al.
patent: 6486008 (2002-11-01), Lee
patent: 6497763 (2002-12-01), Kub et al.
patent: 6534380 (2003-03-01), Yamauchi et al.
patent: 6534382 (2003-03-01), Sakaguchi et al.
patent: 6562703 (2003-05-01), Maa et al.
patent: 6603156 (2003-08-01), Rim
patent: 6649492 (2003-11-01), Chu et al.
patent: 6661065 (2003-12-01), Kunikiyo
patent: 6670677 (2003-12-01), Choe et al.
patent: 6690043 (2004-02-01), Usuda et al.
patent: 2001/0001490 (2001-05-01), Sung et al.
patent: 2002/0125475 (2002-09-01), Chu et al.
patent: 2002/0140031 (2002-10-01), Rim
patent: 2002/0185684 (2002-12-01), Campbell et al.
patent: 2003/0013305 (2003-01-01), Sugii et al.
patent: 2003/0080384 (2003-05-01), Takahashi et al.
patent: 2003/0104287 (2003-06-01), Yuasa
patent: 2003/0227057 (2003-12-01), Lochtefeld et al.
patent: 2003229577 (2003-08-01), None
patent: 2003289144 (2003-10-01), None
Wolf and Tauber “Silicon Processing for the VLSI Era vol. 1 : Process Technology”; pp. 191, 194 and 195; Lattice Press, 1986; Sunset Beach, CA.
Nanocleaving: An Enabling Technologyfor Ultra-thin SOI; Silicon Genesis Corporation; 2002; Japan Society of Applied Physics; pp 97-102.
Current, M.I., et al., “Atomic-Layer Cleaving and Non-Contact Thinning and Thickening for Fabrication of Laminated Electronic and Photonic Materials,” 2001 Materials Research Society Spring Meeting (Apr. 16-20, 2001).
Current, M.I., et al., “Atomic-layer Cleaving with SixGeyStrain Layers for Fabrication of Si and Ge-rich SOI Device Layers,” 2001 IEEE SOI Conference (Oct. 1-4, 2001) pp. 11-12.
Langdo, T.A., et al., “Preparation of Novel SiGe-Free Strained Si on Insulator Substrates,” 2002 IEEE International SOI Conference (Aug. 2002) pp. 211-212.
Mizuno, T., et al., “Novel SOI p-Channel MOSFETs With Higher Strain in Si Channel Using Double SiGe Heterostructures,” IEEE Transactions on Electron Devices, vol. 49, No. 1 (Jan. 2002) pp. 7-14.

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