Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-05-17
2005-05-17
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S933000
Reexamination Certificate
active
06893929
ABSTRACT:
The formation of shallow trench isolations in a strained silicon MOSFET includes implantation of a dopant into overhang portions of the strained silicon layer and silicon germanium layer at the edges of trenches in which shallow trench isolations are to be formed. The conductivity type of the dopant is chosen to be opposite the conductivity type of the source and drain dopants. The implanted dopant increases the threshold voltage Vt beneath the ends of the gate in overhang portions of the strained silicon layer so that it is approximately equal to or greater than that of the remainder of the MOSFET. The resulting strained silicon MOSFET exhibits reduced leakage current beneath the ends of the gate.
REFERENCES:
patent: 6576558 (2003-06-01), Lin et al.
patent: 6590271 (2003-07-01), Liu et al.
patent: 6686255 (2004-02-01), Yang et al.
Lin Ming Ren
Ngo Minh V.
Wang Haihong
Xiang Qi
Advanced Micro Devices , Inc.
Dang Phuc T.
Foley & Lardner LLP
LandOfFree
Method of forming strained silicon MOSFET having improved... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming strained silicon MOSFET having improved..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming strained silicon MOSFET having improved... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3426723