Method of forming stacked insulating film and semiconductor...

Details Method of forming stacked insulating film and semiconductor... Method of forming stacked insulating film and semiconductor...

1998-08-04

2001-03-27

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

Reexamination Certificate

active

06207585

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method of forming a stacked insulating film and a semiconductor device using the same, and particularly to a method of forming a stacked insulating film, which method is suitable for forming a planarized interlayer insulating film on a substrate to be processed on which steps due to interconnections are formed, and a semiconductor device using the same.
With the increased degree of integration of semiconductor devices such as LSIs, there has been extensively used a multilayer interconnection structure, as a result of which a width of an interlayer insulating film between adjacent interconnections in the same interconnection layer has become narrow and a thickness of an interlayer insulating film between different interconnection layers has become thin. Such a reduction in a gap between interconnections causes problems such as an interconnection delay due to the raised capacity between the interconnections. Consequently, the real operating speed of a semiconductor device has come to be not based on the scaling rule of 1/K (K: scaling factor), thus failing to sufficiently obtain a merit of the higher degree of integration. To meet various requirements, for example, high speed operation, low power consumption, and low heat generation of a highly integrated semiconductor device, it is essential to prevent the raised capacity between interconnections.
As an insulating material for forming an interlayer insulating film of a semiconductor device, there has been mainly used an inorganic material such as SiO
2
, SiON or Si
3
N
4
. To reduce a capacity between interconnections in a highly integrated semiconductor device, it is effective to adopt an interlayer insulating film which is made from a material having a low dielectric constant in place of the above-described general inorganic material, as disclosed in Japanese Patent Laid-open No. Sho 63-7650. The material having a low dielectric constant is represented by an inorganic material such as silicon oxide containing fluorine atoms (hereinafter, referred to as “SiOF”) or an organic material containing carbon atoms. The present applicant has disclosed, in Japanese Patent Laid-open No. Hei 8-162528, a technique in which a layer made from a material having a low relative dielectric constant of 3.5 or less is as an interlayer insulating film between adjacent interconnections or between interconnection layers at different levels. In the above document, the present applicant has also proposed a semiconductor device in which an interlayer insulating film having a low dielectric constant and a high reliability is formed of a stacked insulating film having a structure that the above layer made from a material having a low dielectric constant is sandwiched between thin insulating films each having a high quality and being made from such as SiO
2
(relative dielectric constant: 4), SiON (relative dielectric constant: 4 to 6) or Si
3
N
4
(relative dielectric constant: 6)
An interlayer insulating film provided between multilayer interconnections, which is not limited to an insulating film having a low dielectric constant, is required to have a gap fill ability and a global planarization ability for burying recesses between adjacent interconnections. The gap fill ability is an ability of filling a space in a fine gap without occurrence of voids, and the global planarization ability is an ability of filling a large space region without occurrence of unevenness in thickness. As one of methods which have been proposed to meet these requirements, there has been known a so-called APL (Advanced Planarization Layer) technology developed by ETE Corporation in England. In this method, CVD is performed using SiH
4
and H
2
O
2
as a source gas in a state in which a substrate to be processed is cooled to about 0° C., whereby SiO
2
is deposited, as if it is spread in a dropped liquid state, on the surface of the substrate having irregularities. The film of SiO
2
thus obtained has a gap fill ability of sufficiently filling a deep space of an aspect ratio of about 4 and a global planarization ability of sufficiently filling a wide space of 10 &mgr;m without occurrence of unevenness in thickness. In this method, however, when the substrate temperature is increased to 10° C. or more, the behavior similar to that of liquid in the course of film formation is lost, with a result that the gap fill ability and the global planariation ability of the film are gradually degraded.
The APL technology is attractive in terms of the shape of the film as described above; however, it is not effective in terms of formation of a film having a low dielectric constant. That is to say, the film obtained by the APL technology exhibits a relative dielectric constant of 4 to 5 which is at the same level as that of a SOG film or O
3
-TEOS film. This is because a hydroxyl group (—OH group) contained in a planarization insulating film formed by the APL technology (hereinafter, referred to as “APL film”) increases the relative dielectric constant, and if a film of stoichiometric SiO
2
from which the hydroxyl group is removed is formed, the relative dielectric constant of the film is about 3.8 at most.
A method of adding an organic component in an APL film to reduce the dielectric constant of the film has been reported in the 44th Spring Meeting of Association with Applied Physics Institute (p788 in Proceedings, Lecture No. 30p-F-14, 1997). The introduction of an organic component is realized by use of methylsilane (CH
3
)
x
SiH
4-x
(x: natural number of 4 or less) in place of SiH
4
. The mechanism of reducing the dielectric constant of the APL film is considered to be based on the fact that the polarizability of —CH
3
group is small and that the bonding of (—Si—O—Si—) is terminated with —CH
3
group to increase the density of the film. The relative dielectric constant of the APL film formed in accordance with this method is about 3.0.
With respect to each APL film, if used as an interlayer insulating film, it is preferably of a stacked structure with a cap insulating film. The cap insulating film, which is formed on the APL film, has a function of removing an —OH group contained in the APL film by the subsequent heat-treatment to reduce the hardening rate at the hardening stage, thereby preventing occurrence of cracks. The cap insulating film is formed by plasma CVD using SiH
4
and N
2
O as a source gas because it can exhibit a function of preventing occurrence of particles in a vapor phase and also it must be formed at a temperature lower than the heat-treatment temperature. In the above method of forming a cap insulating film, however, ammonia produced from nitrogen and hydrogen generated by dissociation of SiH
4
and N
2
O in plasma is absorbed on or trapped in the APL film, which exerts adverse effect on characteristics of an element containing the ALP film.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of forming a stacked insulating film having an excellent flatness and a high reliability without occurrence of ammonia, particles and cracks by a liquid phase CVD, for example, based on the APL technology, and a highly integrated semiconductor device with a high reliability using the above stacked insulating film as an interlayer insulating film.
To achieve the above object, according to a first aspect of the present invention, there is provided a method of forming a stacked insulating film, including the sequential steps of: forming a planarization insulating film containing an —OH group on a substrate to be processed by a chemical vapor deposition process using a source gas containing either an inorganic silane compound gas or an organic silane compound gas and an oxidizer having an —OH group; forming a cap insulating film on the planarization insulating film using a source gas containing an inorganic silane compound gas, an oxidizer, and a hydrocarbon; and removing the —OH group contained in the planarization insulating film by heat-treatment.
The hydrocarbon is preferably at l

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