Method of forming spacers in CMOS devices

Details Method of forming spacers in CMOS devices Method of forming spacers in CMOS devices

2001-05-04

2003-06-03

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S231000, C438S303000, C438S199000, C438S369000, C438S268000, C257S328000

Reexamination Certificate

active

06573133

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates a semiconductor fabrication technique, and in particular to a method of forming spacers in CMOS devices.
2. Description of the Prior Art
In the fabrication of CMOS devices, a polysilicon gate is typically deposited over a gate oxide grown on the silicon substrate. Ion implantation occurs through the field oxide located between the gates. In order to protect the gate region during the implantation step, the side walls of the gates are protected with vertical walls known as spacers. In the past, amorphous silicon was used for the spacers, but this created problems during subsequent etching in that it was difficult to avoid over-etching and the removal of part of the underlying layer. Over-etching occurs when etching extends into the underlying layer. Often when the spacers were removed, a polysilicon gate would be etched at the same time leaving a notch, known as a “mouse bite” in the polysilicon gate.
An object of the invention is to alleviate this problem.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, the side wall spacers are made of silicon nitride. Silicon nitride has the advantage of offering good selectivity, making it easy to avoid over-etching when the precursor conformal layer is removed.
In accordance with an important aspect of the invention, a conformal silicon nitride layer is etched using a chlorine-based plasma etch chemistry. Such etch chemistry consists of chlorine (Cl
2
), hydrogen bromide (HB
r
), and a mixture of helium and oxygen. This is in contrast to the conventional CHF
3
chemistry, which is normally used for silicon nitride etching. The applicants have found that using conventional silicon nitride etch chemistry, it is very difficult to avoid over-etching into the gate oxide because of the high plasma power and the limited oxide
itride selectivity of 1.8 to 1.
In accordance with the present invention, it has been found surprisingly that oxide
itride selectivities in the order of 3 to 1 can be achieved, which completely protects the gate oxide. In the invention the etching is caused largely by chemical rather than the mechanical interaction associated with CHF
3
plasmas. The Cl
−
radicals etch the silicon nitride chemically and the HBr component is responsible mainly for mechanical etching by the plasma. The reaction of HBr with silicon nitride also creates a protective polymer layer that protects the more vertical profiles of the etched films, resulting in a more anisoptropic etch. Some spacers are left along the polysilicon lines with a rounded shape.
While the etch rate using chlorine-based etch chemistry, typically around 2000 Angstroms per minute, is somewhat slower than CHF
3
—based chemistry, typically around 5000 Angstroms per minute, this trade-off is more than offset by the improvement in selectivity obtainable.
The conformal nitride layer is preferably deposited onto a thin oxide layer, typically about 200 Angstroms thick.


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