Method of forming source and drain regions in complementary MOS

Details Method of forming source and drain regions in complementary MOS Method of forming source and drain regions in complementary MOS

1998-09-29

2000-07-25

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438230, 438202, 438203, 438207, H01L 218238

Patent

active

060935952

ABSTRACT:
A method of forming a complementary metal-oxide-semiconductor (CMOS) integrated circuit, and the integrated circuit so formed, are disclosed. After the formation of a p-type well (4) and an n-type well (6) into which the transistors are to be formed; and gate structures (8n, 8p) overlying the surfaces of these wells (4, 6), a doped insulating layer (20) is formed overall, for example by way of chemical vapor deposition. The doped insulating layer (20) is, according to the preferred embodiment of the invention, silicon dioxide that is doped with boron. In the preferred embodiment of the invention, the portion of the doped insulating layer (20) overlying the p-type well (4) is removed, and ion implantation of n-type dopant is then performed. The remaining portion of the doped insulating layer (20) protects the n-type well (6) from the n-type ion implantation steps. The structure is then heated to diffuse dopant from the doped insulating layer (20) into n-type well (6) at its surface, in a self-aligned manner relative to the gate structure (8n) thereat. The process provides a CMOS structure that can be fabricated with at least one fewer photolithography operation than in conventional methods.

REFERENCES:
patent: 4843023 (1989-06-01), Chiu et al.
patent: 5006477 (1991-04-01), Farb
patent: 5015595 (1991-05-01), Wollensen
patent: 5024959 (1991-06-01), Pfiester
patent: 5956591 (1999-09-01), Fulford

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