Method of forming silicon oxide layer in semiconductor...

Details Method of forming silicon oxide layer in semiconductor... Method of forming silicon oxide layer in semiconductor...

2001-11-05

2002-11-12

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S784000, C438S787000, C438S790000, C438S359000

Reexamination Certificate

active

06479405

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a silicon oxide layer using a spin-on glass (SOG) composition useful in forming a silicon oxide layer in a semiconductor manufacturing process. More particularly, the present invention relates to a method of forming a silicon oxide layer applied as an insulating layer in a semiconductor manufacturing process using a spin-on glass composition including perhydro-polysilazane.
2. Description of the Prior Art
The design of semiconductor devices has been progressing rapidly. In particular, this progress has required semiconductor devices to function with high operating speed, and to have a large storage capacitance. In order to satisfy such requirements, semiconductor devices with increased density, reliability, and response time are under development.
Integrated circuits are typically manufactured by forming a large number of active devices on a single substrate. After each device is formed and insulated, some of the devices are electrically interconnected during the manufacturing process to accomplish a desirable circuit function. Metal Oxide Semiconductor (MOS) and bipolar VLSI and ULSI devices, for example, have multilevel interconnection structures in which a large number of devices are interconnected. In such a multilevel interconnection structure, the topography of the top layer usually becomes increasingly irregular and uneven as the number of layers increases.
For example, a semiconductor wafer with two or more metal layers is typically formed as follows. A number of oxide layers, a polycrystalline silicon conductive layer, and a first metal wiring layer are formed on a semiconductor wafer. A first insulation layer is then formed on the resulting structure. Then, a via hole is formed for providing circuit paths to a second metal layer. At this time, the surface of the first insulation layer is uneven because the layers underlying the first insulation layer are uneven. When the second metal layer is directly formed on the first insulation layer, the second metal layer may fracture due to protrusions or cracks in the underlying insulation layer. In addition, there may be a decreased yield of the semiconductor device if the deposition state of the metal layer is poor. Accordingly, the insulation layer is typically planarized before formation of the via hole or the second metal layer that will be formed in a multilevel metal interconnection structure.
Various methods have been developed to planarize the insulation layer. These methods include utilizing a borophosphorous silicate glass (BPSG) layer, which has good reflow characteristic, or an SOG layer and a chemical mechanical polishing (CMP) method. In general, BPSG is widely utilized as an insulation layer material to fill gaps between metal wirings. However, depositing BPSG presents problems because it depends primarily on establishing special deposition parameters for the equipment utilized. In addition, the gases used in the process are expensive and severely toxic.
Furthermore, as the packing density increases and the design rule gradually decreases for manufacturing VLSI having 256 megabits or more, using BPSG as the insulation layer to fill gaps between wirings lowers the yield due to the occurrence of voids and bridges. In addition, an etch stop layer may be damaged during its subsequent formation. Thus, the prior art typically implements a reflowing process and an expensive CMP process to solve these problems.
An insulation layer formed by an SOG layer is known in the art as being manufactured by a simple coating process. This process produces a planar insulation layer. For example, U.S. Pat. No. 5,310,720 (issued to Shin et al.) discloses a method for making a silicon oxide layer. A polysilazane layer is formed, and then the polysilazane layer is heated in an oxygen atmosphere to convert it into a silicon oxide layer. U.S. Pat. No. 5,976,618 (issued to Shunichi Fukuyama et al.) discloses a method in which an inorganic SOG is deposited, and then two step heat treatment processes are implemented to convert the SOG layer into a silicon oxide layer.
The basic backbone structure of polysilazane-based SOG is composed of Si—N, Si—H and N—H bonds. The Si—N bonds are converted into (or substituted with) Si—O bonds by baking under an atmosphere including oxygen and water. A simple spin coating and a simple curing process are performed to convert the SOG layer into the silicon oxide layer. Accordingly, it is an economical method.
Not all of the Si—N bonds, however, are converted to Si—O bonds (see, for example, Japanese Patent Laid-Open No. Hei 11-145286). Accordingly, the silicon oxide layer has different insulating and electrical characteristics when compared to a pure silicon oxide layer such as one formed using a BPSG layer or a TEOS layer. For these reasons, using SOG to form a layer, and then convert it into a silicon oxide insulation layer has been avoided. In addition, because SOG is deposited by a spin coating method, the thickness of the thus formed silicon oxide layer is not sufficient to provide adequate coverage for conductive layers, such as gate electrodes and metal wirings.
The Applicants of the present invention have invented a spin-on glass composition including perhydropolysilazane providing the ability to bury a gap between metal wirings of VLSI degree having a high aspect ratio, bury a gap on a substrate without the need to apply a mechanical planarization, smooth surface discontinuities, and produce an oxide layer of a semiconductor device. The spin-on glass composition has substantially the same characteristics as an oxide layer of a semiconductor device formed by a chemical vapor deposition (CVD) method.
The Applicants of the present invention have accordingly filed a patent application, which is now pending, entitled: “SPIN-ON GLASS COMPOSITION AND METHOD OF FORMING SILICON OXIDE LAYER IN SEMICONDUCTOR MANUFACTURING PROCESS USING THE SAME,” with the USPTO as Ser. No. 09/686,624, on Oct. 12, 2000.
According to an embodiment of this method, a planar SOG layer is formed on a semiconductor substrate having a stepped portion or surface discontinuities by coating on the semiconductor substrate a spin-on glass composition including polysilazane having the chemical formula of —(SiH
2
NH
2
)
n
— where n represents a positive integer, a weight average molecular weight within the range of about 4,000 to 8,000, and a molecular weight dispersion degree within the range of about 3.0 to 4.0. Finally, the SOG layer is cured to form a silicon oxide layer having a planar surface.
As for the silicon oxide layer, an isolation layer of an STI (shallow trench isolation) structure that may be formed on a semiconductor substrate having a stepped portion formed by grooves and protrusions may be illustrated to form an isolation structure.
The baking step is implemented by two steps of a pre-baking and a main-baking. The pre-baking of the SOG layer is implemented at a temperature within a range of about 100-500° C., more preferably within a range of about 100-400° C., for a period of about 1-5 minutes, and more preferably, for a period of about 2-3 minutes. The main-baking of the SOG layer is implemented at a temperature within a range of about 900-1,050° C.
At this time, the manufactured silicon oxide layer has a good gap filling characteristic for an STI structure including gaps having about 0.1-1 &mgr;m. However, according to a wet etching rate test, the etching rate decreases as the temperature of the main-baking increases, and a silicon oxide layer is formed at the surface portion of the silicon substrate and an active region.
FIG. 1
illustrates a cross-sectional view of an oxide formed on an inner surface of a trench. The device illustrated in
FIG. 1
is manufactured by the following method. A pad oxide layer is formed on a silicon substrate
100
and then, a nitride layer and a high temperature oxide layer are sequentially formed on the pad oxide layer. The nitride layer is provided as an etch stopping layer for t

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