Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-01-08
2003-04-29
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
Reexamination Certificate
active
06555442
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor fabrication and more specifically to methods of forming shallow trench isolation (STI) structures.
BACKGROUND OF THE INVENTION
Shallow trench isolation (STI) has become the most common and important isolation technology for sub-quarter micron complimentary metal oxide semiconductor (CMOS) devices. The edge treatment of STI is one of the key issues to suppress the corner effects and to maintain gate oxide integrity. Issues such as edge leakage, inverse narrow channel effect and “humps” in Id-Vg curves become critical as the isolation pitch is scaled down.
The conventional STI process flow includes pad oxide and chemical vapor deposition (CVD) silicon nitride (SiN) deposition, active area masking, nitride/oxide etching, silicon (Si) trench etching, liner oxidation, high density plasma (HDP) oxide filling, chemical mechanical polishing (CMP) polishing, and nitride and pad oxide removal.
Well known issues in conventional STI processes include corner rounding and divot formation (i.e. oxide recess) along STI edges. The divot at the edge of the STI is formed due to wet dip of pad oxide by an HF solution. Although the liner oxidation can round the corner of the STI edge, the degree of rounding may not be enough.
Several techniques have been developed to reduce the divot slightly by etching the edge of the nitride layer (referred to as “pull-back”) after the silicon trench formation (but before liner oxidation). The corner is then exposed and becomes more rounded and thicker by the oxide growth by the subsequent liner oxidation. Another technique adds a poly-buffer layer in between the pad oxide and nitride (referred to as poly-buffer STI) so that the corner can become more rounded during liner oxidation. The poly-buffer layer also can reduce the stress from the nitride to the substrate. The pull-back and poly-buffer techniques may even be combined to result in even greater enhanced performance of STIs.
U.S. Pat. No. 6,228,747 B1 to Joyner, U.S. Pat. No. 5,801,083 to Yu et al. and U.S. Pat. No. 5,679,599 to Mehta each describe a disposable spacer in an STI and a rounded corner process.
U.S. Pat. No. 4,707,218 to Giammarco et al. describes a disposable spacer in an STI process.
U.S. Pat. No. 6,074,932 to Wu describes a related STI process.
U.S. Pat. No. 5,933,749 to Lee describes a process to round the top trench corner in an STI process.
The article entitled “Shallow Trench Isolation for advanced ULSI CMOS Technologies,” N. Nandakumar et al., IEDM, 1998, pages 98-133 to 98-126, describes requirements in designing an STI process flow for 0.1 &mgr;m CMOS technologies. Various processing techniques are described for the steps in the STI flow, that is trench definition, corner rounding, gapfill, planarization and well implants.
The article entitled “New Corner Rounding Process for Sub-0.15 &mgr;m Shallow Trench Isolation,” W. G. Kim et al., IEDM, 1999, pages 133 to 135, describes the evaluation of a process to obtain a top corner rounding in STI processes.
The article entitled “Advanced Shallow Trench Isolation to Suppress the Inverse Narrow Channel Effects for 0.24 &mgr;m Pitch Isolation and Beyond,” K. Horita et al., IEEE, 2000, pages 178 and 179, describes a STI technique named Poly-Si-Buffered-mask STI (PB-STI) using an SiN/poly-Si/O
2
stacked mask.
SUMMARY OF THE INVENTION
Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of forming shallow trench isolation (STI) structures.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a silicon structure having a pad oxide layer formed thereover is provided. An undoped poly buffer layer is formed over the pad oxide layer. A hard mask layer is formed over the undoped poly buffer layer. The hard mask layer, the undoped poly buffer layer and the pad oxide layer are patterned to form an opening exposing a portion of the silicon structure within an active area. The opening having exposed side walls. Inorganic spacers are formed over the exposed side walls. Using the patterned hard mask layer and the spacers as hard masks, the silicon structure is etched to form an STI opening within the active area. The inorganic spacers are removed exposing the upper corners of the STI opening. Using an oxidation process, a liner oxide layer is formed within the STI opening, over the upper corners of the STI opening and at least the patterned undoped poly buffer layer exposed by the removal of the inorganic spacers. An STI oxide layer is formed over the patterned hard mask layer, filling the liner oxide layer lined STI opening. The STI oxide layer is planarized and the patterned hard mask, the patterned undoped poly buffer layer and the patterned pad oxide layer are removed to fabricate the STI having rounded corners and without substantial divots.
REFERENCES:
patent: 4707218 (1987-11-01), Giammarco et al.
patent: 5679599 (1997-10-01), Mehta
patent: 5801083 (1998-09-01), Yu et al.
patent: 5933749 (1999-08-01), Lee
patent: 6074932 (2000-06-01), Wu
patent: 6228747 (2001-05-01), Joyner
patent: 6274420 (2001-08-01), Xiang
patent: 6413828 (2002-07-01), Lam
patent: 6432797 (2002-08-01), Frost et al.
“Shallow Trench Isolation for Advanced ULSI CMOS Technologies,” N. Nandakumar et al., IEDM, 1998, pp. 98-133 to 98-126.
“New Corner Rounding Process for Sub-0.15&mgr;m Shallow Trench Isolation,” W. G. Kim et al., IEDM, 1999, pp. 133-135.
“Advanced Shallow Trench Isolation to Suppress the Inverse Narrow Channel Effects for 0.24&mgr;m Pitch Isolation and Beyond,” K. Horita et al., IEEE, 2000, pp. 178-179.
Chi Min-Hwa
Pai Chih-Yang
Tsai Chia-Shiung
Tu Yeur-Luen
Yu Chih-Hsing
Ackerman Stephen B.
Cuneo Kamand
Nguyen Trung
Saile George O.
Stanton Stephen G.
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