Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-10
2002-01-15
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S404000, C438S424000, C438S425000
Reexamination Certificate
active
06339004
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a method of forming a trench for semiconductor device isolation and, more particularly, to a method of forming a shallow trench for semiconductor device isolation which exhibits good performance characteristics, and is well adapted for serving in device miniaturization.
(b) Description of the Related Art
Generally, a local oxidation of silicon (LOCOS) technique has been used for device isolation purpose in the semiconductor fabrication process.
In the LOCOS technique, the silicon wafer itself is thermally oxidized while using a nitride for a mask, and requires only a small number of processing steps. For this reason, the resulting oxide involves lower degree of stress, and exhibits good insulating characteristics.
However, in the application of the LOCOS technique, the device isolation area takes a large volume that limits device miniaturization as well as involves occurrence of the so-called bird's beak.
In order to solve the above problems, a shallow trench isolation (STI) technique has been suggested.
In the STI technique, a shallow trench is made in the silicon wafer, and filled with an insulating material. In this structure, the device isolation area is small, and hence the resulting trench can be well adapted for device miniaturization.
FIGS. 1A
to
1
D schematically illustrate the steps of processing a trench for device isolation according to a prior art.
As shown in
FIG. 1A
, a silicon wafer
1
is thermally oxidized so that a pad oxide
2
with a thickness of 100-200 Å is grown at the silicon wafer
1
. A nitride
3
with a thickness of 1000-2000 Å is deposited onto the pad oxide
2
through low pressure chemical vapor deposition (LPCVD). The pad oxide
2
and the nitride
3
are patterned through photolithography, and the exposed silicon wafer
1
is etched such that a shallow trench is formed at the device isolation area.
As shown in
FIG. 1B
, the silicon wafer
1
is thermally oxidized so that a liner oxide
4
is grown at the inner wall of the trench. A trench-filling oxide
5
with a thickness of 8000-11000 Å is deposited onto the entire surface of the silicon wafer
1
through atmospheric chemical vapor deposition (APCVD) such that the trench is completely buried by the trench-filling oxide
5
. The silicon wafer
1
is then annealed at 900-1000 ° C. for 20-50 minutes under a nitrogen gas (N
2
) atmosphere to thereby density the trench-filling oxide
5
.
As shown in
FIG. 1C
, the densified trench-filling oxide
5
is patterned through photolithography such that it is left only at the trench area.
As shown in
FIG. 1D
, the trench-filling oxide
5
at top side of the trench is removed through chemical mechanical polishing (CMP) while utilizing the nitride
3
as a stopping layer during the polishing. That is, the trench-filling oxide
5
is planarized such that the top portion of the trench-filling oxide
5
is level with the nitride
3
. In this way, the formation of a shallow trench for device isolation is completed.
However, the above-described trench formation technique bears complicated processing steps. Furthermore, when the trench-filling oxide
5
is planarized through the CMP, the top edge portion of the trench-filling oxide
5
cracks so that the trench-filling oxide
5
remaining after the planarization is torn (usually called the “torn oxide”), causing serious device failures.
Furthermore, among the impurities used in the CMOS transistor, boron-like components that exhibit a high diffusion property at high temperatures are diffused toward the trench during annealing or thermal oxidation and can induce an electrical short or leakage, deteriorating device reliability.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of forming a trench for device isolation which has simplified processing steps, avoids the tom oxide phenomenon, and ensures device reliability.
These and other objects may be achieved by a method of forming a trench for semiconductor device isolation including the following steps. A trench is first made at a device isolation area of a silicon wafer by etching the silicon wafer through a mask pattern. A liner oxide is then formed on the silicon wafer and within the trench through thermal oxidation, and a nitride layer is formed on the liner oxide through low pressure chemical vapor deposition. The nitride is anisotropically dry-etched such that the nitride is left only at the sidewall of the trench. A trench-filling oxide is then deposited onto the entire surface of the silicon wafer through high pressure chemical vapor deposition, and annealed. The trench-filling oxide is planarized through chemical mechanical polishing until the top surface of the trench-filling oxide layer is positioned slightly over the liner oxide on the silicon wafer. The silicon wafer is then wet-cleaned, and thermally oxidized such that a pad oxide is grown at the surface of the silicon wafer.
The thickness of the liner oxide is established to be 150-400 Å, and that of the nitride to be 300-1000 Å. The thickness of the pad oxide is 100-200 Å.
REFERENCES:
patent: 4404236 (1983-09-01), Komatsu et al.
patent: 6040231 (2000-03-01), Wu
patent: 6046106 (2000-04-01), Tran et al.
patent: 6074927 (2000-06-01), Kepler et al.
patent: 6165854 (2000-12-01), Wu
patent: 6177332 (2001-01-01), Chen et al.
patent: 6251735 (2001-06-01), Lou
patent: 6277706 (2001-08-01), Ishikawa
patent: 57-154855 (1982-09-01), None
patent: 62-151047 (1986-12-01), None
Bothra et al., “Integration of 0.25 &mgr;m Three and Five Level Interconnect System For High Performance ASIC”, Proceedings Fourteenth International VLSI Multilevel Interconnection Conference, Jun. 1997, pp. 5, 43-48.
Liu et al., “Integrated HDP Technology for Sub-0.25 Micron Gap Fill”, Proceedings Fourteenth International VLSI Multilevel Interconnection Conference, Jun. 1997, pp. 618-619, 695.
Nguyen et al., “Characterization of High Density Plasma Deposited Silicon Oxide Dielectric For 0.25 Micron ULSI”, Proceedings Twelfth International VLSI Multilevel Interconnection Conference, Jun. 1995, pp. 5, 59-75.
Saikawa et al., “High Density Plasma CVD For 0.3 &mgr;m Device Application”, Proceedings Thirteenth International VLSI Multilevel Interconnection Conference, Jun. 1996, pp. 5, 69-74.
Schwartz et al., “Chemical Vapor Deposition Reactors”,Handbook of Semiconductor Interconnection Technology, 1998, Chapter I, Section 3.3, pp. vii, 6-9.
Wang et al., “Process Window Characterization of Ultima HDP-CVD™”, Proceedings Third International Dielectrics For ULSI Multilevel Interconnection Conference (DUMIC), Feb. 1997, pp. 5-7, 405-408.
AnAm Semiconductor Inc.
Jones Josetta I.
Niebling John F.
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