Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-11-18
1998-11-17
Bowers, Charles
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438258, 438263, 438264, H01L 21336
Patent
active
058375830
ABSTRACT:
An EEPROM with separated floating gate to reduce the antenna ratio is disclosed. The structure of the EEPROM includes field oxides formed on a wafer. A control gate is formed in the wafer. A first gate oxide formed above the wafer for isolation. A first polysilicon portion is formed on the first gate oxide, which includes a gate for a transistor, a first contact window and a floating gate. Further, the floating gate is set above the control gate. A second gate oxide is formed on the wafer adjacent to the field oxide for isolation. A tunneling window is formed in the second gate oxide. A second polysilicon portion having a second contact window is formed on the second gate oxide. A dielectric layer is formed on the first polysilicon portion and the second polysilicon portion. Contact holes are formed in the dielectric layer and a connecting structure formed in the contact holes and on the dielectric layer for interconnection.
REFERENCES:
patent: 4162176 (1979-07-01), Tsuda
patent: 5296397 (1994-03-01), Lee
Chuang K.-J.
Lui H.-S.
Bowers Charles
Chen Jack
Taiwan Semiconductor Manufacturing Co. Ltd.
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