Method of forming semiconductor memory device with LDD

Details Method of forming semiconductor memory device with LDD Method of forming semiconductor memory device with LDD

1999-07-16

2001-11-27

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S213000, C438S231000, C438S232000, C438S279000, C438S305000, C438S306000, C438S514000, C438S527000, C438S529000

Reexamination Certificate

active

06323091

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a ROM (read only memory) having a high breakdown voltage and a high threshold voltage.
BACKGROUND OF THE INVENTION
ROM devices include memory cells for storing data, and peripheral circuitry to control the read operation from the memory cells. A memory cell stores a bit of data. Specifically, each memory cell composed of an N-type transistor has a threshold voltage indicating each bit of the data. For example, a high threshold voltage corresponds to a “1” bit, and a low threshold voltage corresponds to a “0” bit.
There are various methods for manufacturing ROMs. For example, U.S. Pat. No. 5,538,914 (Chiu et al.) describes a method for manufacturing a ROM device having LDD (lightly doped drain) regions. The method of Chiu et al. uses two programming masks for an NLDD (N-type lightly doped drain) implant and a PLDD (P-type lightly doped drain) implant. Since the method of Chiu et al. requires two programming masks to be modified based on the data, the method results in higher manufacturing cost and complexity.
U.S. Pat. No. 5,407,852 (Ghio et al.) also describes a manufacturing method of a ROM device. However, the method of Ghio et al. also uses two photoresist masks for ROM programming. Namely, a photoresist mask M
1
in FIG.
2
of Ghio et al., and a ROM protection photoresist mask M
2
in
FIG. 4
of Ghio et al. should be modified in accordance with the data to be programmed. Therefore, Ghio et al. does not improve the complexity and cost of manufacturing associated with the two mask programming.
SUMMARY OF THE INVENTION
The present invention provides a method for manufacturing a semiconductor device which requires only a single mask for ROM programming. The present invention also provides a semiconductor device in which ROM programming is performed by forming a PLDD region between a source region and a gate region of a programmed cell.
According to one aspect of the present invention, ROM programming ion implantation is performed by the same mask as one used for implanting dopant in MOS transistors of a peripheral region. The ROM programming ion implantation is concurrently conducted with formation of the MOS transistors in the peripheral region. As a result, only a single mask needs to be modified for the ROM programming, with no masks added. Thus, the present invention reduces cost and complexity of manufacturing the device.
According to another aspect of the present invention, a programmed cell of the present invention has a PLDD region between a source region and a gate region of a memory cell, and has a NLDD region between a drain region and the gate region of the memory cell. Since the PLDD region adjacent to the source contributes to a high threshold voltage, and the NLDD region adjacent to the drain contributes to a high breakdown voltage, the device of the present invention exhibits balanced characteristics suitable for a ROM device.
According to another aspect of the present invention, a programmed cell of the present invention has PLDD regions between a source region and a gate region of a memory cell, and between a drain region and the gate region of the memory cell. Since the PLDD region adjacent to the source contributes to a high threshold voltage, the device of the present invention exhibits characteristics suitable for a ROM device. Further, the device is immune to programming mask misalignment since, in a programmed cell, an edge of the programming mask does not need to be on the gate structure.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.


REFERENCES:
patent: 5407852 (1995-04-01), Ghio et al.
patent: 5538914 (1996-07-01), Chiu et al.
patent: 5716885 (1998-02-01), Kim et al.
patent: 5776806 (1998-07-01), Dennison et al.
patent: 6329578 (1988-02-01), None
patent: 289163 (1996-10-01), None

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