Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-27
2002-05-07
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S250000, C438S393000, C438S766000, C438S952000, C438S966000
Reexamination Certificate
active
06383859
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, which includes a step of forming an anti-reflection coating film for the purpose of increasing fabrication accuracy in the step of photolithography, and a semiconductor device made by this manufacturing method. More specifically, the invention relates to a semiconductor device manufactured by integrating a capacitor and a transistor on a semiconductor substrate, and a manufacturing method of the same.
2. Description of the Prior Art
FIGS. 1
to
3
are sectional views showing a conventional method for manufacturing a semiconductor device having a capacitor and a MOS (Metal Oxide Semiconductor) transistor in the sequence of steps.
First, as shown in
FIG. 1A
, a field oxide film
62
is formed in a device isolation region of a semiconductor substrate
61
by means of LOCOS (Local Oxidation of Silicon). Also, a gate oxide film
63
is formed on the surface of a transistor forming region of the semiconductor substrate
61
with thermal oxidation.
Subsequently, a polycrystalline silicon film
64
is formed on a surface of the semiconductor substrate
61
so as to serve as a lower electrode of a capacitor (referred to as a capacitor lower electrode, hereinafter) and a gate electrode of a transistor. Then, by introducing high-concentration impurities (dopant) to the polycrystalline silicon film
64
, electrical conductivity is provided.
Then, a silicon oxide film
65
is formed as a dielectric film of the capacitor (referred to as a capacitor dielectric film, hereinafter) on the polycrystalline silicon film
64
, and a polycrystalline silicon film
66
is formed thereon so as to serve as an upper electrode of the capacitor (referred to as a capacitor upper electrode, hereinafter). Then, by introducing high-concentration impurities to the polycrystalline silicon film
66
, electrical conductivity is provided.
Then, as shown in
FIG. 1B
, a resist pattern
67
is formed on the polycrystalline silicon film
66
so as to plot a shape of the capacitor upper electrode. Then, by using this resist pattern
67
as a mask, etching is performed for the polycrystalline silicon film
66
and the silicon oxide film
65
to form a capacitor dielectric film
65
a and a capacitor upper electrode
66
a.
Subsequently, the resist pattern
67
is removed.
Then, as shown in
FIG. 2A
, an anti-reflection coating film
68
is formed on a surface of the semiconductor substrate
61
. The polycrystalline silicon film
64
and the capacitor upper electrode
66
a
are covered with the anti-reflection coating film
68
. The anti-reflection coating film
68
is then coated with photoresist. After the photoresist is subjected to exposure and development, a resist pattern
69
is formed so as to plot shapes of a capacitor lower electrode and a gate electrode of the MOS transistor.
Then, as shown in
FIG. 2B
, by using the resist pattern
69
as a mask, etching is performed for the anti-reflection coating film
68
and the polycrystalline silicon film
64
to form a capacitor lower electrode
64
a
and a gate electrode
64
b.
Subsequently, the resist pattern
69
is removed. Then, shallow and low-concentration impurities are ion-implanted to both sides of the gate electrode
64
b
of the semiconductor substrate
61
to form an LDD (Lightly Doped Drain) diffused layer
70
in self-alignment.
Then, a silicon oxide film is formed to be thick on a fill surface above the semiconductor substrate
61
, and anisotropic etching is performed for this silicon oxide film. Accordingly, as shown in
FIG. 3A
, the silicon oxide film is left in the sides of the capacitor lower electrode
64
a,
the capacitor upper electrode
66
a
and the gate electrode
64
b
to form spacers
71
. Subsequently, impurities are ion-implanted at relatively high concentration to both sides of the gate electrode
64
b
of the semiconductor substrate
61
to form impurity diffused regions
72
as a source and a drain of the MOS transistor in self-alignment.
Then, as shown in
FIG. 3B
, the anti-reflection coating film
68
on the capacitor upper electrode
66
a,
the capacitor lower electrode
64
a
and the gate electrode
64
b
is removed. Subsequently, an interlayer insulating film, a wiring (not shown), and so on, are formed to complete a semiconductor device having the capacitor and the MOS transistor of an LDD structure.
Along with the demand for much higher integration of a semiconductor device in recent years, a gate electrode or the like of a MOS transistor has tended to be shrunk. Thus, a KrF light source or an ArF light source has been used as a light source to be used in a photolithography. Also, for an anti-reflection coating film effective when any one of these light sources is used, a silicon nitride film (SiN) or a silicon oxynitride film (SiON) which is silicon-rich has been used.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device capable of preventing an insulation failure caused by an anti-reflection coating film, and preventing damage to a MOS transistor or a capacitor in etching step during spacer formation by leaving the anti-reflection coating film until spacers are formed. It is another object of the invention to provide a method for manufacturing the above semiconductor device.
In order to achieve the object, as specified in claim 1 and shown in
FIG. 7
, a semiconductor device of the invention comprises: a capacitor element; and an electrical field effect transistor. In this case, the capacitor includes a capacitor lower electrode (
14
a
) formed on a semiconductor substrate (
11
) by interpolating an insulating film (
12
), a capacitor dielectric film (
15
a
) formed on the capacitor lower electrode (
14
a
), a capacitor upper electrode (
16
a
) formed on the capacitor dielectric film (
15
a
) so as to have a shape smaller than that of the same, and an anti-reflection coating film (
19
) formed on the capacitor dielectric film (
15
a
) exposed to the outside of the upper electrode (
16
a
).
In order to achieve the object, as specified in claim 3 and shown in
FIGS. 4
to
7
, a manufacturing method of the semiconductor device having the capacitor and the transistor comprises the steps of: forming first insulating films (
12
and
13
) on a semiconductor substrate (
11
); forming a first conductive film (
14
) on the first insulating films (
12
and
13
); forming a second insulating film (
15
) on the first conductive film (
14
); forming a second conductive film (
16
) on the second insulating film (
15
); forming an upper electrode (
16
a
) of the capacitor by performing pattering for the second conductive film (
16
); forming a dielectric film (
15
a
) of the capacitor below the upper electrode (
16
a
) so as to have a shape larger than that of the same by performing patterning for the second insulating film (
15
); forming an anti-reflection coating film (
19
) on a full surface above the semiconductor substrate (
11
); forming a resist pattern (
20
) by coating the anti-reflection coating film (
19
) with photoresist and then subjecting the photoresist to exposure and development, the resist pattern being used to plot shapes of a lower electrode of the capacitor and a gate electrode of the transistor; forming a lower electrode (
14
a
) of the capacitor and a gate electrode (
14
b
) of the transistor by using the resist pattern (
20
) as a mask to perform patterning for the anti-reflection coating film (
19
) and the first conductive film (
14
); removing the anti-reflection coating film (
19
) remaining on the upper electrode (
16
a
) of the capacitor and the gate electrode (
14
b
) of the transistor after the resist pattern (
20
) is removed; and forming a source and a drain (
23
) of the transistor by introducing impurities to both sides of the gate electrode (
14
b
) of the semiconductor substrate (
11
).
In order to achieve the object, as specified in claim 8 and shown in
FIGS. 11
to
13
, a manufacturing method of the semiconduct
Armstrong Westerman & Hattori, LLP
Everhart Caridad
Fujitsu Limited
Lytle Craig P.
LandOfFree
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