Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-01-18
2004-03-30
Nguyen, Thanh (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S613000, C438S627000, C438S638000, C438S648000, C438S687000
Reexamination Certificate
active
06713381
ABSTRACT:
FIELD OF THE INVENTION
This invention relates in general to processes for forming semiconductor devices, and more particularly to processes for forming semiconductor devices including interconnect barrier layers.
RELATED ART
Forming conductive bumps over semiconductor device bond pads is becoming increasingly common as the sizes and packages of the semiconductor devices continue to shrink. The bumps are used instead of wires to electrically connect the bond pads to their respective packaging leads. One specific type of bump includes a controlled-collapse chip-connection (C4) bump. Bumps generally require that a pad limiting metal layer be formed between the bond pad and the bump. Pad limiting metal layers typically include chrome and chromium alloys. However, these chromium-containing films can have defects, such as cracks and irregular grain boundaries, which limit the ability of the chromium layer to adequately separate the bond pad and the bump materials.
The bump typically includes elements such as tin (Sn) and lead (Pb). In the event the barrier fails to keep the bond pad and the bump separated, material from the bond pad can react with the lead or tin in the bump and intermetallic alloys of these materials can be formed. If the bond pad includes a copper-containing material, a brittle intermetallic alloy can be the result. The brittle intermetallic alloy can subsequently crack and result in bump failure. In addition, voids can form as a result of the alloying process and degrade adhesion between the bond pad and the bump. In extreme cases this can produce high resistance that can negatively impact the semiconductor device's performance and even result in failure of the semiconductor device.
REFERENCES:
patent: 5220199 (1993-06-01), Owada et al.
patent: 5470787 (1995-11-01), Greer
patent: 5656858 (1997-08-01), Kondo et al.
patent: 5686760 (1997-11-01), Miyakawa
patent: 5731624 (1998-03-01), Motsiff et al.
patent: 5767010 (1998-06-01), Mis et al.
patent: 5904556 (1999-05-01), Suzuki et al.
patent: 6187680 (2001-02-01), Costrini et al.
patent: 6255151 (2001-07-01), Fukuda et al.
Colgan, “Selective CVD-W for Capping Damascene Cu Lines,” Elsevier Science S.A., Thin Solid Films 262, pp. 120-123 (1995).
Marcadal, et al., “CVD Process for Copper Interconection,” Elsevier Science B.V., Microelectronic Engineering 37/38, pp. 97-103 (1997).
Mori, et al., “Metal Capped Cu Interconnection Technology by Chemical Mechanical Polishing,” VMIC Conference, ISMIC, Jun. 18-20, pp. 487-492 (1996).
Adetutu Olubunmi
Anthony Brian G.
Barr Alexander L.
Braeckelmann Gregor
Clegg David B.
Balconi-Lamica Michael J.
Motorola Inc.
Nguyen Thanh
Rodriguez Robert A.
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