Method of forming self-passivating interconnects and...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C257S737000

Reexamination Certificate

active

11081187

ABSTRACT:
A method of forming self-passivating interconnects. At least one of two mating bond structures is formed, at least in part, from an alloy of a first metal and a second metal (or other element). The second metal is capable of migrating through the first metal to free surfaces of the mating bond structures. During bonding, the two mating bond structures are bonded together to form an interconnect, and the second metal segregates to free surfaces of this interconnect to form a passivation layer. Other embodiments are described and claimed.

REFERENCES:
patent: 2004/0108363 (2004-06-01), Giraudet
patent: 2004/0219763 (2004-11-01), Kim et al.
patent: 2004/0232537 (2004-11-01), Kobrinsky et al.
patent: 2004/0262772 (2004-12-01), Ramanathan et al.
patent: 2005/0003650 (2005-01-01), Ramanathan et al.
patent: 2005/0003652 (2005-01-01), Ramanathan et al.
patent: WO 2005/001933 (2005-01-01), None
PCT Search Report Dated Aug. 10, 2006.
K-A Son et al., “Growth and Oxidation of Thin Film A12Cu”, Journal of Electrochemical Society, vol. 148, No. 7, 2001, pp. B260-B263.
K. Banerjee et al., “3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration”.
Proc. of the IEEE, New York, US, vol. 89, No. 5, May 2001, pp. 602-633.
Pending U.S. Appl. No. 10/683,202, not yet published, filed Oct. 9, 2003 to Patrick Morrow et al.

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