Method of forming self-aligned unlanded via holes

Details Method of forming self-aligned unlanded via holes Method of forming self-aligned unlanded via holes

1999-07-06

2001-02-13

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S623000, C438S639000

Reexamination Certificate

active

06187668

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming self-aligned unlanded via holes of integrated circuits, and more particularly to a process of forming self-aligned unlanded via holes by depositing an HDP-CVD dielectric layer and a silicon nitride layer within.
2. Description of the Prior Art
The current trend in VLSI design toward denser and more complex circuitry produces closely spaced and smaller geometries on larger wafers, which results in narrower and longer interconnect lines. The increase of circuit density has obviously improved the performance of electric devices by reducing RC delay time and effectively decreased the cost. However, one of the limitations in a VLSI process is the size of a via hole (or via plug) which is formed for connecting two conductive layers. How to exactly define a smaller via hole to a proper position is a challenging issue for a VLSI fabrication.
The size of a via hole is usually smaller than the metal line width for avoiding the problem of misalignment induced during a step of photolithography. Please referring to
FIG. 1
, a cross-sectional view of part of a partially fabricated integrated circuit structure with via plugs according to the prior art is illustrated, the misalignment of via holes could induce a problem of over-etch to damage the first dielectric layer
100
a
and even the devices beneath. As a result, the misaligned via plugs
60
b
will be a problem of electric short.
Therefore, a self-aligned contact (SAC) process of forming via holes is developed for decreasing the size of each via hole with the misalignment problem.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of forming self-aligned unlanded via holes, wherein a silicon nitride layer is formed for the self-aligning process.
Another object of the present invention is to provide a method of forming self-aligned unlanded via holes for allowing the minimizing of mis-alignment in a photolithography step to increasing throughout.
In accordance with the objects of this invention, there is shown a method of forming self-aligned unlanded via holes. First, a substrate having a patterned conductive layer on its surface is provided, and then a first dielectric layer is deposited on the substrate by using high density plasma chemical vapor deposition (HDP CVD). Next, a silicon nitride layer and a second dielectric layer are sequentially deposited on the first dielectric layer. Thereafter, the second dielectric layer, the silicon nitride layer and the first dielectric layer are etched back to remove a portion of the silicon nitride layer overlying the patterned conductive layer. Finally, a third dielectric layer is deposited, and then via holes are defined in the third dielectric layer.


REFERENCES:
patent: 5989967 (1999-11-01), Gardner et al.
patent: 6030896 (2000-02-01), Brown
patent: 6037211 (2000-03-01), Jeng et al.
patent: 6054394 (2000-04-01), Wang

Affiliated with

Also associated with

Rating

Method of forming self-aligned unlanded via holes does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming self-aligned unlanded via holes, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming self-aligned unlanded via holes will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2614777