Method of forming self-aligned stacked capacitor

Details Method of forming self-aligned stacked capacitor Method of forming self-aligned stacked capacitor

2001-10-05

2002-07-02

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S398000, C438S964000, C438S396000, C438S253000

Reexamination Certificate

active

06413817

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of forming a self-aligned stacked capacitor.
2. Description of Related Art
Capacitor is one of the principle components in dynamic random access memory (DRAM). To prevent the storage of erroneous data in a DRAM unit and increase operating efficiency, a large area capacitor such as a crown capacitor is generally used in each DRAM cell. As the level of integration in DRAM increases, the need for larger surface area in each capacitor is urgent. One common method of increasing surface area of a capacitor is to place the capacitor and bit line on separate layers within a wafer resulting in a stacked type capacitor structure. In general, according to the position of the capacitor and the bit line, DRAM capacitors can be divided into a ‘bit line on capacitor’ (BOC) and a ‘capacitor on bit line’ (COB) type. However, the COB type is the more common DRAM capacitor type of the two.
FIGS. 1A
,
1
C,
2
,
3
and
4
are schematic cross-sectional views showing the steps for forming a convention COB type of DRAM stacked capacitor. As shown in
FIG. 1A
, a substrate
100
is provided. The substrate
100
has isolation layers
110
, gate oxide layers
120
, word lines
130
, a common source region
140
and a drain regions already formed thereon. The common source region
140
is formed between two word lines
130
, the drain regions
150
are formed on one side of the word lines
130
and the isolation layers
110
are formed just outside the drain regions
150
. A silicon oxide layer
155
is formed over the substrate
100
, and then bit line contacts
160
and node contacts
170
are formed in the silicon oxide layer
155
. A bit line
180
is formed over the silicon oxide layer
155
. The bit line
180
is electrically connected with a bit line contact
160
.
FIG. 1B
is a top view of the structure shown in FIG.
1
A. In fact,
FIG. 1A
is a cross-sectional view along line I—I of FIG.
1
B. As shown in
FIG. 1B
, the node contacts
170
are formed between two bit lines
180
.
FIG. 1C
is a cross-sectional view along line II—II of FIG.
1
B. As shown in
FIG. 1C
, another portion of the isolation layers
110
is formed on each side of the drain regions
150
.
As shown in
FIG. 2
, a silicon oxide layer
190
is deposited over the substrate
100
. Photolithographic and etching processes are next carried out to form a node contact opening
192
in the silicon oxide layer
190
. A silicon nitride (SiN) liner layer
194
is formed on the sidewalls of the node contact opening
192
. The liner layer
194
prevents short-circuiting between the subsequently formed second-stage node contact and the bit line
180
.
As shown in
FIG. 3
, a polysilicon layer
210
is formed over the substrate
100
. The polysilicon layer
210
completely fills the node contact opening
192
to form a node contact
200
. The polysilicon layer
210
is patterned by photolithographic and etching processes.
As shown in
FIG. 4
, photolithographic and etching processes are carried out to pattern the polysilicon layer
210
to form the lower electrode
210
a
of a crown capacitor. Hemispherical silicon grains
220
are grown over the exposed surface of the crown-shaped lower electrode
210
a
so that surface area is increased. Finally, a conformal oxide
itride/oxide composite layer
230
and a polysilicon layer
240
are sequentially formed over the lower electrode
210
a
to form a complete crown-shaped capacitor. The polysilicon layer
240
functions as the upper electrode of the crown-shaped capacitor.
However, the aforementioned method of forming a stacked capacitor has several drawbacks. Photolithographic and etching operations are required to pattern out both the lower electrode (patterning the polysilicon layer
210
in
FIG. 3
) as well as the outline of the crown-shaped lower electrode
210
a
(shown in FIG.
4
). Hence, processing complexity is increased. In addition, if the alignment error of the lower electrode is large so that contact area between the polysilicon layer
210
and the node contact
200
is too small, a portion of the polysilicon layer
210
may shed. The shed polysilicon micro-particles can become a source of pollutants.
In the manufacturing of a conventional stacked capacitor as shown in
FIG. 4
, the lower electrode
210
a
of a crown-shaped capacitor has a height of about 8.5 KÅ. Thus, in any subsequent etching step for forming a contact opening, the process must face a large aspect ratio that may lead to etching stop.
Another drawback is the need to form a silicon nitride liner
194
as shown in
FIGS. 2 and 3
. Due to the relative closeness between the node contact
200
and the bit line
180
, short-circuiting between the node contact
200
and bit line
180
can be common if there is any alignment error. Therefore, the formation of an insulating liner layer
194
between the node contact
200
and the bit line
180
is essential.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of forming a self-aligned stacked capacitor capable of reducing processing complexity, pollution due to micro-particles and a high aspect ratio.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a self-aligned stacked capacitor on a substrate having a first insulation layer thereon. A bit line contact and a first section node contact are formed in the first insulation layer, and then a bit line structure is formed over the first insulation layer. The bit line structure includes a bit line, a cap layer and spacers. The bit line and the bit line contact are electrically connected. The cap layer is formed above the bit line while the spacers are formed on the sidewalls of the bit line and the cap layer.
A second insulation layer, an etching stop layer and a third insulation layer are sequentially formed over the substrate. An opening is formed in the third insulation layer, the etching stop layer and the second insulation layer. The opening exposes a portion of the bit line structure and the first section node contact. A conformal first conductive layer is formed over the interior surface of the opening. The lower section of the first conductive layer forms a second section node contact as well as the lower portion of the crown-shaped lower electrode. The upper section of the first conductive layer is the crown portion of the lower electrode. The first conductive layer is formed by depositing conductive material over the substrate to form a conformal conductive layer, and then removing the conductive material outside the opening by chemical-mechanical polishing. Finally, a conformal dielectric layer and a second conductive layer are sequentially formed over the substrate. The second conductive layer forms the upper electrode of the crown-shaped capacitor.
An additional step of growing hemispherical silicon grains over the surface of the crown-shaped lower electrode can be conducted after forming the crown-shaped lower electrode but before forming the dielectric layer and the second conductive layer.
Furthermore, after the formation of the crown-shaped lower electrode, an additional step of removing the third insulation layer can be performed. The third insulation layer can be removed by wet etching, for example. Moreover, after the removal of the third insulation layer, a step for forming hemispherical silicon grains over the exposed surface of the crown-shaped lower electrode can be inserted.
This invention also provides a stacked capacitor structure formed by the aforementioned self-aligned method. The structure is formed above a substrate having a first insulation layer thereon. The structure includes a bit line contact, a first section node contact, a bit line structure, a second insulation layer, an etching stop layer, a second section node cont

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