Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-17
2001-10-16
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S217000, C438S425000, C438S433000
Reexamination Certificate
active
06303417
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of forming a twin-well for CMOS (Complementary Metal-Oxide-Semiconductor) transistors, and more particularly, to a method of forming a self-aligned planarization twin-well for CMOS transistors by using fewer mask counts than conventional skills.
2. Description of the Prior Art
In the present days, CMOS transistors construct more and more devices because the CMOS structures offer a lot of advantages such as low power consumption than NMOS and PMOS transistors. For example, the CMOS transistors draw very little current during the transition from one state to another, and allow power consumption to be minimized. However, the aforementioned advantages are important attributes for high-density applications.
Typically, there are many technologies used to fabricate the CMOS transistors, such as p-well, n-well, and twin-well processes. As noted, the twin-well process is the most attractive scheme utilized for fabricating CMOS products because many advantages offered by the twin-well technology. The twin-well technology fabricates two separate twins to be implemented into very lightly doped silicon. This also allows the doping profiles in each twin region to be tailored independently so that neither type of device will suffer from excessive doping effects. Furthermore, the doping profile of each of the device types can be set independently since the constraint of single-well CMOS does not exist.
All persons skilled in the art know that a planar surface should be prepared before performing sequence processes of forming CMOS transistors. Unfortunately, it is difficult to obtain a true planarized self-aligned twin-well for CMOS transistors because the twin boundary has a topography height, which usually varies from 100 to 200 nm (nano meters). Under this situation with such a topography height, the current I-line lithography tools encounter severe difficulties when printing transistors with dimension below 0.35 &mgr;m. Accordingly, this disadvantage becomes a bottleneck especially for deep sub-micro ULSI (Ultra-Large-Scale-Integrated) applications that are the main electronic products today (please refer to “0.2-&mgr;m n-Channel and p-Channel MOSFET's Integrated on Oxidation-Planarized Twin-Tubs” in IEEE Electron Device Lett., vol., EDL-11, p. 500-502, 1996.) Also, for gate runners parallel to the topography edges, ragged lines are formed due to proximity effects in the resist exposure. Therefore, for the lithography of deep sub-micro window contact that contains more topography from the gate runners, the variation becomes even more server. A requirement has been arisen to disclose a process for overcoming the aforementioned disadvantages while fabricating CMOS transistors.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts.
Accordingly, the present invention discloses a method of preparing a planarized self-aligned twin-well for CMOS transistors. After a silicon nitride layer is formed over a pad oxide layer on a semiconductor substrate, an N-well region is defined by first implanting in the semiconductor substrate. After removing the first photoresist layer, a second ion implantation is performed to define a P-well region. Next, both the silicon nitride layer and the pad oxide layer are removed. A high temperature steam oxidation process is then performed to remove the crystalline defects, and the in-situ high temperature long time anneal is done to form a deep twin-well. A plurality of trenches is formed to define an active area region, and a LPD oxide layer is then formed and refilled in said trenches. An etching back process is performed to remove a portion of the LPD oxide layer above top surface of the substrate. A second pad oxide layer is formed on the substrate. Finally, the standard processes can be employed for fabricating the CMOS transistors.
REFERENCES:
patent: 5445989 (1995-08-01), Lur et al.
patent: 5453395 (1995-09-01), Lur
Lindsay Jr. Walter L.
Moga, Esq. Thomas T.
Niebling John F.
Powell Goldstein Frazer & Murphy LLP
TSMC-Acer Semiconductor Manufacturing Corp.
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