Method of forming self aligned contacts

Details Method of forming self aligned contacts Method of forming self aligned contacts

2000-09-14

2004-10-12

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S735000

Reexamination Certificate

active

06803318

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to improved methods for etching openings in insulating layers and a semiconductor device with well defined contact openings.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
In the fabrication of semiconductor devices, numerous conductive device regions such as transistors and layers of devices may be formed in or on a semiconductor substrate. For example, a typical metal oxide semiconductor (MOS) transistor such as a NMOS or PMOS transistor generally includes source/drain regions in a substrate, and a gate electrode formed above the substrate between the source/drain regions and separated from the substrate by a relatively thin dielectric. Conductive regions and layers of the device may be isolated from one another by a dielectric. Examples of dielectrics may include silicon dioxide (SiO
2
), tetraorthosilicate glass (TEOS), silicon nitride (Si
x
N
y
), silicon oxynitride (SiO
x
N
y
(H
2
)), and silicon dioxide/silicon nitride/silicon dioxide (ONO) The dielectrics may be grown or may be deposited by physical deposition such as sputtering or by a variety of chemical deposition methods and chemistries such as chemical vapor deposition. Additionally, the dielectrics may be undoped or may be doped, for example with boron, phosphorus, boron and phosphorus, or fluorine, to form a doped dielectric layer such as borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), and fluorinated silicate glass (FSG).
At various stages in the fabrication of semiconductor devices, it may be necessary to form openings in a dielectric layer to allow for contact to underlying regions or layers. Generally, an opening through a dielectric exposing a diffusion region or an opening through a dielectric layer between polysilicon and a first metal layer is called a “contact opening” or a “contact hole.” An opening in other dielectric layers such as an opening through an intermetal dielectric layer is referred to as a “via.” For purposes of this disclosure, henceforth “contact opening” may be used to refer to a contact opening and/or a via. A contact opening may expose a diffusion region within the silicon substrate such as a source or drain, or may expose some other layer or structure such as an underlying metallization layer, a local interconnect layer, or a gate structure. Conductive contact structures may be formed above the source/drain regions, and interconnects may overlie the contact structures and may connect neighboring contact structures. These contact structures to diffusion regions may be isolated from an adjacent gate structure by a dielectric spacer or dielectric shoulder portions. The dielectric spacer or dielectric shoulder portions may also isolate the gate from the diffusion region.
There are, however, disadvantages associated with typical conductive contact structures. For example, conductive contact structures may be aligned to the underlying regions or layers with a masking step such as a lithography process. Therefore, extra area may be allocated to prevent misalignment of the contact structure to the underlying regions or layers. Proper alignment is necessary to avoid shorting the contact structure to other underlying structures such as a gate or a diffusion well surrounding a diffusion region having an overlying contact structure. As such, typical contact structures may limit any reduction in area of the underlying regions or layers such as diffusion regions. In this manner, larger contact areas may limit the density of elements which may be formed on a semiconductor device. Larger contact areas may also be responsible for increased diffusion-to-substrate junction capacitance, which may limit the speed of a semiconductor device.
A self aligned contact structure may eliminate alignment problems associated with typical contact structures and may increase the device density of a structure. A self aligned contact structure may be a contact to a source or drain diffusion region. A self aligned contact structure may be useful in compact semiconductor device geometries because the self aligned contact structure may overlap a conducting area such as a gate structure to which it is not supposed to make electric contact and the edge of a diffusion region without shorting out to the well beneath. Consequently, less contact area may be needed and gates or conductive material lines such as polysilicon lines may be moved closer together. As such, more gates or lines may be formed on a given substrate than with typical contact structures.
As the device densities of semiconductor devices are continually being increased, profile and dimension requirements of semiconductor device features such as self aligned contact structures must be further optimized. For example, typically it is desirable for a contact opening to have sidewalls which are substantially perpendicular to an upper surface of a semiconductor substrate. As such, the sidewall angle of the contact opening may be at a 90° angle with respect to the upper surface of the semiconductor substrate such that lateral dimensions of the contact opening may be substantially uniform across the height of the contact opening. In this manner, a contact structure may be formed in the contact opening which may have predictable and desirable dimensions and electrical properties. In addition, the lateral dimensions of semiconductor features such as self aligned contact structures are continually being reduced in order to increase the device density on a semiconductor substrate. Generally, however, the height of semiconductor features may not be reduced in proportion to the lateral dimensions. In this manner, the aspect ratio of semiconductor features such as contact structures may be higher for advanced semiconductor devices which may be designed to have high device densities. An aspect ratio as used herein generally describes the ratio between the height and width of a semiconductor feature such as a contact structure when viewed in cross section. As the aspect ratio of a contact structure increases, it may become increasingly difficult to form the contact opening. For example, if the sidewall angle of the contact opening deviates substantially from 90°, the lateral dimensions of the contact opening at the top of the contact opening may be larger than an acceptable critical dimension before the entire contact opening may be formed.
To form such a self aligned contact opening a patterned layer of photoresist may be formed over the dielectric layer having openings corresponding to regions of the dielectric layer where contact openings are to be formed in the dielectric layer. In most modern processes, a dry etch may then be performed in which the wafer may be exposed to a plasma. The plasma may be formed by flowing one or more gases such as one or more halocarbons and/or one or more other halogenated compounds such as CF
4
, CHF
3
(Freon 23), SF
6
, and NF
3
. In addition, gases such as O
2
, Ar, and N
2
may also be added to the gas flow. After the opening has been formed thereby exposing a portion of the region or layer to be contacted, the opening may be cleaned with a sputter etch such as a radio-frequency sputter etch. The sputter etch may be used to remove small amounts of material which may form on sidewalls or a bottom surface of the contact opening during dry etching of the contact opening. The opening may then be filled with a conductive material which may be deposited in the opening and in electrical contact with the underlying region or layer. The conductive material may be planarized such that an upper surface of the conductive material is substantially coplanar with an upper surface of the dielectric layer thereby forming a self aligned contact structure.
There are, however, several disadvantages to conventional methods for forming self aligned contact structures. For example, typically a conta

Affiliated with

Also associated with

Rating

Method of forming self aligned contacts does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming self aligned contacts, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming self aligned contacts will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3309354