Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-07-09
2001-03-20
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S258000, C438S593000
Reexamination Certificate
active
06204159
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to simplified methods of making flash memory devices such as EEPROMs. More particularly, the present invention relates to simplified methods of making NAND type flash memory devices characterized by improved select gate performance.
BACKGROUND ART
Semiconductor devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art
FIG. 1
a,
a memory device such as a flash memory
10
comprises one or more high density core regions
11
and a low density peripheral portion
12
on a single substrate
13
. The high density core regions
11
typically consist of at least one M×N array of individually addressable, substantially identical floating-gate type memory cells and the low density peripheral portion
12
typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
The memory cells within the core portion
11
are coupled together in a NAND-type circuit configuration, such as, for example, the configuration illustrated in prior art
FIG. 1
b.
Each memory cell
14
has a drain
14
a,
a source
14
b
and a stacked gate
14
c.
A plurality of memory cells
14
connected together in series with a drain select transistor at one end and a source select transistor at the other end to form a NAND string as illustrated in prior art
FIG. 1
b.
Each stacked gate
14
c
is coupled to a word line (WL
0
, WL
1
, . . . , WLn) while each drain of the drain select transistors are coupled to a bit line (BL
0
, BL
1
, . . . , BLn). Lastly, each source of the source select transistors are coupled to a common source line Vss. Using peripheral decoder and control circuitry, each memory cell
14
can be addressed for programming, reading or erasing functions.
Prior art
FIG. 1
c
represents a fragmentary cross section diagram of a typical memory cell
14
in the core region
11
of prior art
FIGS. 1
a
and
1
b.
Such a cell
14
typically includes the source
14
b,
the drain
14
a
and a channel
15
in a substrate or P-well
16
; and the stacked gate structure
14
c
overlying the channel
15
. The stacked gate
14
c
further includes a thin gate dielectric layer
17
a
(commonly referred to as the tunnel oxide) formed on the surface of the P-well
16
. The stacked gate
14
c
also includes a polysilicon floating gate
17
b
which overlies the tunnel oxide
17
a
and an interpoly dielectric layer
17
c
overlies the floating gate
17
b.
The interpoly dielectric layer
17
c
is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate
17
d
overlies the interpoly dielectric layer
17
c.
The control gates
17
d
of the respective cells
14
that are formed in a lateral row share a common word line (WL) associated with the row of cells (see, for example, prior art
FIG. 1
b
). In addition, as highlighted above, the drain regions
14
a
of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel
15
of the cell
14
conducts current between the source
14
b
and the drain
14
a
in accordance with an electric field developed in the channel
15
by the stacked gate structure
14
c.
The process for making such NAND type flash memory devices includes numerous individual processing steps. Each flash memory device must be fabricated in the same manner as other flash memory devices to provide consistent performance and reliability. Generally speaking, the fewer the number of processing steps, the easier it is to fabricate uniform flash memory devices.
For example, fabricating the select gate transistors and the flash memory cells in the core region of NAND type flash memory devices is complicated and involves numerous processing steps. Conventional fabrication techniques involve initially growing a select gate oxide over the entire core region or substrate, providing a tunnel oxide mask over the select gate areas, etching the exposed oxide, removing the tunnel oxide mask, cleaning the substrate, and growing a tunnel oxide layer. The process may further involve various inspection and evaluation steps after one or more of the numerous processing steps.
There are several concerns with such a process. For instance, there is a high defect density associated with using the tunnel oxide mask. A so-called Poly 1 contact is undesirably employed as a select gate interconnect. As a result, excessively high or low Poly 1 doping levels affect device performance (charge gain/loss problems). Residual oxides are common place, leading to diminished electrical properties.
In view of the aforementioned concerns and problems, there is a need for flash memory cells of improved quality and more efficient methods of making such memory cells.
SUMMARY OF THE INVENTION
As a result of the present invention, non-volatile flash memory device fabrication is not only simplified, but devices having improved reliability are obtainable. By employing the simplified methods of the present invention which eliminate the use of steps associated with using a tunnel oxide mask, forming a flash memory device having a low defect density, minimized charge gain/loss concerns from high/low Poly 1 doping, and fewer select gate interconnection problems is facilitated.
In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a core region and a periphery region, the core region including a flash memory cell area and a select gate area and the periphery region including a high voltage transistor area and low voltage transistor area; depositing a first doped amorphous silicon layer over at least a portion of the first oxide layer; depositing a dielectric layer over at least a portion of the first doped amorphous silicon layer; removing portions of the first oxide layer, the first doped amorphous silicon layer, and the dielectric layer in the select gate area of the core region and the high voltage transistor area and the low voltage transistor area the periphery region; growing a second oxide layer over at least a portion of the substrate in the select gate area of the core region and the high voltage transistor area and the low voltage transistor area the periphery region; removing portions of the second oxide layer in the select gate area of the core region and the low voltage transistor area the periphery region; growing a third oxide layer over at least a portion of the substrate in the select gate area of the core region and the low voltage transistor area of the periphery region; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer, the second oxide layer and the third oxide layer; and forming a flash memory cell in the flash memory cell area of the core region, a select gate transistor in the select gate area of the core region, a low voltage transistor in the low voltage transistor area of the periphery region, and a high voltage transistor in the high voltage transistor area of the periphery region.
In another embodiment, the present invention relates to a method of forming a flash memory cell and a select gate of a NAND type flash memory device, involving the steps of growing a first oxide layer having a thickness from about 70 Å to about 110 Å over at least a portion of a substrate, the substrate including a core region, the core region including a flash memory cell area and a select gate area; depositing a first doped amorphous silicon layer over at least a portion of the first oxide layer; depositing a dielectric layer
Au Kenneth Wo-Wai
Chang Kent Kuohua
He Yue-song
Advanced Micro Devices , Inc.
Fourson George
Garcia Joannie A.
Renner , Otto, Boisselle & Sklar, LLP
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