Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
1999-09-14
2001-08-28
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C438S315000, C438S142000, C438S257000, C438S258000, C438S259000, C438S297000, C438S309000, C257S300000, C257S301000, C257S304000, C257S305000
Reexamination Certificate
active
06281089
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the fabrication of flash memory devices and more particularly to an embedded flash memory without composite tunnel oxide layer.
BACKGROUND OF THE INVENTION
Memory technology has progressed considerably in recent years. Since the operational speed and the manipulation data amount of a central processing unit (CPU) is increasing, the performance of a memory cell is increasing at the same time. For example, high speed erasing is a popular method for improving the performance of a memory. Volatile storage memories such as random access memory (RAM) is widely used in computer nowadays. But the stored data vanishes due to the power break off. Another nonvolatile storage memories such as mask read only memory (Mask ROM), erasable programmable ROM (EPROM), or electrically erasable programmable ROM (EEPROM) will not lost the stored messages when lack of power and will be better for some specific usage.
Flash memories are also a nonvolatile storage memory with similar structure as EEPROMs. They have a very high speed erasing feature in either an overall region or a local region thereof, therefore they are very popular in the computer field also. For example, they are used to replace the read-only memories to store the firmware such as BIOS (basic input/output system). The users can easily update their BIOS by rewriting the flash memory.
Conventional flash memory cells have a double or triple layer of polysilicon structure. The upper most polysilicon layer is patterned to form the control gates and the word lines of the structure, and the second polysilicon layer is patterned to form the floating gates as a double layer structure. A third polysilicon layer is patterned as select gates to form the triple layer polysilicon structure. No matter what the structures of the flash memories are, the characteristic of tunnel oxide layer between the substrate and the floating gate is a key factor for the operation of flash memories.
Although the scale down of devices is the trend for semiconductor fabrication, the flash memories cannot scale down the thickness of tunnel oxide in order to avoid leakage current problem. For example, the thickness of tunnel oxide between about 90 to 100 angstroms will be used in 1.0 &mgr;m generation as well as 0.25 &mgr;m generation.
Alternatively, there are configurations of single-poly flash memories together with logic circuitry. When embedding memory cells into a standard logic process, it is desirable to do so without changing the single-poly process typically used in the fabrication of the logic circuitry. This desire has led to the development of a single-poly flash memory cell having the same N+ source and drain regions formed in a P type substrate. An N diffusion region formed in the P type substrate serves as the control gate and is capacitively coupled to the floating gate via a thin oxide layer. That is, tunnel oxide layer. Since the control gate and floating gate of this singly-poly flash cell form a capacitor in a manner similar to that of the more traditional stacked-gate, double-poly, or triple-poly flash cells, the single-poly flash cell is programmed, erased, and read in a manner similar to that of the conventional flash cell.
Furthermore, when we fabricate the semiconductor devices above 0.5 &mgr;m generation, the thickness of gate oxide layer of the logic cell is thicker than tunnel oxide layer of embedded flash cell. Accordingly, the tunnel oxide layer of embedded flash cell can be grown last together with the gate oxide layer of the logic cell. A high quality tunnel oxide layer can be achieved easily due to one step processing. Nevertheless, when the periphery logic cell is scale down due to cost saving and lower power consumption, the thickness of gate oxide layer can be formed from, for example, about 130 A at 0.5 &mgr;m generation and reduced to about 70 A at 0.35 &mgr;m generation. The typical thickness of the logic gate oxide layer at 0.35 &mgr;m generation is thinner than the normal tunnel oxide layer thickness (between about 90~100 angstroms) and the tunnel oxide last grown would not work. Prior art techniques introduce composite tunnel oxide to solve this problem but it will degrade the quality and cycling performance of tunnel oxide. Another approach is to compromise the periphery circuit performance and use the thicker gate oxide. (e.g. 95 A) To compromise between the logic cell and the flash cell, the standard logic cell library cannot be implemented since it is not a truly embedded flash cell.
SUMMARY OF THE INVENTION
The present invention is directed to the fabrication of single-poly flash memory cell. Due to the disadvantage of fabricating processes when the devices are scaling down for embedded flash memory cell, it is a principal object of the present invention to provide a method for embedded single-poly flash cell fabrication with a high quality tunnel oxide layer when the dimensions of the periphery devices are diminished.
It is another object of the present invention to provide a method for embedded single-poly flash memory cell fabrication with high reliability and cost saving of the devices.
Firstly, a lightly doped P-type substrate with <100> crystallographic orientation is provided. Next, use thermal oxidation to grow a pad oxide layer and a silicon nitride layer on the substrate. After silicon nitride layer etching, a relatively thick field oxide layer is formed and active areas are defined. The active areas are separated into three areas, the first sense area is used for logic cell, the second tunnel oxide window area and the third capacitor coupling area are used for single-poly flash memory.
Subsequently, a conventional photolithography and etching method is used to form a patterned photoresist over the substrate and expose the areas for flash cell, that is, tunnel oxide window and capacitor coupling area. Then, N-type conductive dopants such as arsenic ions and phosphorus ions are used to implant into the substrate. For 0.35 &mgr;m generation, the concentration of dopant is increased to about 5E17~1E19 atoms/cm
3
. Next, the patterned photoresist layer is removed by dry and wet etching steps. The pad oxide layer is then removed by diluted hydrofluoric acid (HF) solution. Thereafter, dry oxidation of O
2
oxidant is used to grow the tunnel oxide and gate oxide simultaneously, then a thicker tunnel oxide layer between about 90~100 angstroms and a thinner gate oxide layer between about 65~75 angstroms are formed due to the dopant effect. Next, a doped polysilicon layer is deposited by using a conventional chemical vapor deposition over the tunnel oxide layer to serve as the floating gate of the flash cell.
With the processing steps of the present invention, the complexity of the embedded flash memory processes will not increase due to the scaling down of the logic cells, therefore cost is not increased and yield is not reduced. Besides, a high quality tunnel oxide layer is maintained.
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Shirai et al. “a 0.54 micron Self-aligned HSG gate cell for Flash Memories” IEEE 1995 IEDM 95-653(0-7803-2700-4).*
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Lee Granville D
Smith Matthew
Worldwide Semiconductor Manufacturing Corp.
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