Method of forming poly tip of floating gate in split-gate...

Details Method of forming poly tip of floating gate in split-gate... Method of forming poly tip of floating gate in split-gate...

2002-11-13

2003-11-25

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S259000, C438S593000, C257SE29129

Reexamination Certificate

active

06653188

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority to Taiwan Patent Application No. 091109603 entitled “Method for Forming Poly Tip of Floating Gate in Split Gate Flash Memory”, filed May 8, 2002.
FIELD OF INVENTION
The present invention generally relates to a method of forming floating gate, and more particularly, to a method of forming a poly tip of floating gate in a split-gate memory.
BACKGROUND OF THE INVENTION
The structure of a flash memory cell is classified into two types, a stacked-gate structure and a split-gate structure. Due to the over-erasure phenomenon, the stacked-gate transistor easily becomes a depletion transistor, which conducts even in absence of the application of a control voltage at the control gate. The split-gate memory is devised to overcome the over-erasure problem of the stacked-gate type memory.
Referring to
FIG. 1
, a split-gate memory device
10
includes a floating gate
12
covering a portion of the channel region. The control gate
14
directly controls the rest of the channel. When memory cells are arranged in such configuration, the transistor solely controlled by the control gate
14
is free from influence of the state of floating gate
12
. Therefore, the memory cell can maintain its correct state irrespective of the over-erasure problem.
The speed of programming and erasing a flash memory device is an important criterion for the performance of a memory device. A faster erase speed is achieved if the coupling ratio between the control gate and the floating gate is low. In other words, by having a thinner. floating gate as well as a sharper edge on the gate, the erase speed is increased. Therefore, forming a floating gate with sharp poly tip is a desire approach of developing the split-gate flash memory.
As shown in
FIG. 1
, the method for forming a conventional floating gate tip includes the step of sequentially forming a gate oxide layer
18
, a polysilicon layer
12
serving as the floating gate, and a silicon nitride layer on a silicon substrate
16
. Then, by ways of photolithography and etch techniques, an opening defining the floating gate is formed in the nitride layer. The key aspect of the conventional method is the thermal oxidation of the polysilicon layer
12
to form a silicon oxide layer
20
. Then, the nitride layer and the polysilicon layer
12
thereunder are removed by using the silicon oxide layer
20
as an etching mask. In the subsequent steps, an interpoly oxide layer
22
and the control gate
14
are formed to complete the formation of the split-gate memory
10
.
Due to the utilization of thermal oxidation to form the oxide layer, which is removed in a later step, the conventional floating gate tip shape is determined by the oxidation of the polysilicon layer
20
. Therefore, there is a need to provide a method of forming a shaper tip or a tip with well-controlled shape to increase the erase speed of a split-gate flash memory device.
OBJECTS AND SUMMARY OF THE INVENTION
One aspect of the present invention is to provide a method of forming a poly tip of a floating gate to increase the erase speed of a split-gate memory.
It is another aspect of the present invention that a method of forming a floating gate tip is provided, which employs a poly spacer to form a shaper and better-controlled tip.
It is a further aspect of the present invention that a method for forming a floating gate tip is provided, which forms a spacer for better control of the tip shape and the process parameters.
The method includes the step of providing a semiconductor substrate with a gate dielectric layer formed on the semiconductor substrate. A first polysilicon (or poly) layer is then formed on the gate dielectric layer. A hard mask layer is formed on the first polysilicon layer. Then, an opening is formed in the hard mask layer to expose a portion of the first polysilicon layer. Next, a poly spacer is formed in the opening. Then, the hard mask layer and the first polysilicon layer thereunder are removed to form the floating gate.
The method further includes the step of thermal oxidizing the first polysilicon layer and the poly spacer to sharpen the poly spacer. The method further includes the step of forming an interpoly insulating layer and a control gate layer to form a split-gate flash memory.


REFERENCES:
patent: 6093945 (2000-07-01), Yang
patent: 6204126 (2001-03-01), Hsieh et al.

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