Method of forming ono stacked films and DCS tungsten...

Details Method of forming ono stacked films and DCS tungsten... Method of forming ono stacked films and DCS tungsten...

1998-12-04

2002-04-30

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S261000

Reexamination Certificate

active

06380029

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to flash memory devices such as EEPROMs. More particularly, the present invention relates to flash memory devices exhibiting increased charge coupling ratio, reduced thickness of the multilayer insulator and increased gate oxide reliability.
BACKGROUND ART
Nonvolatile memory devices include flash EEPROMs (electrical erasable programmable read only memory devices).
FIG. 1
represents the relevant portion of a typical flash memory cell
10
. The memory cell
10
typically includes a source region
12
, a drain region
14
and a channel region
16
in a substrate
18
; and a stacked gate structure
20
overlying the channel region
16
. The stacked gate
20
includes a thin gate dielectric layer
22
(commonly referred to as the tunnel oxide) formed on the surface of the substrate
18
. The stacked gate
20
also includes a polysilicon floating gate
24
which overlies the tunnel oxide
22
and an interpoly dielectric layer
26
which overlies the floating gate
24
. The interpoly dielectric layer
26
is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers
26
a
and
26
b
sandwiching a nitride layer
26
c.
A polysilicon control gate
28
overlies the interpoly dielectric layer
26
and a conductive layer
30
, such as a tungsten silicide layer, overlies the polysilicon control gate
28
. The conductive layer
30
may constitute, in part, a word line. The channel region
16
of the memory cell
10
conducts current between the source region
12
and the drain region
14
in accordance with an electric field developed in the channel region
16
by the stacked gate structure
20
.
Generally speaking, a flash memory cell is programmed by inducing hot electron injection from a portion of the substrate, such as the channel section near the drain region, to the floating gate. Electron injection carries negative charge into the floating gate. The injection mechanism can be induced by grounding the source region and a bulk portion of the substrate and applying a relatively high positive voltage to the control electrode to create an electron attracting field and applying a positive voltage of moderate magnitude to the drain region in order to generate “hot” (high energy) electrons. After sufficient negative charge accumulates on the floating gate, the negative potential of the floating gate raises the threshold voltage (V
th
) of its field effect transistor (FET) and inhibits current flow through the channel region through a subsequent “read” mode. The magnitude of the read current is used to determine whether or not a flash memory cell is programmed. The act of discharging the floating gate of a flash memory cell is called the erase function. The erase function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source region of the transistor (source erase or negative gate erase) or between the floating gate and the substrate (channel erase). A source erase operation is induced by applying a high positive voltage to the source region and a 0 V to the control gate and the substrate while floating the drain of the respective memory cell.
Referring still to
FIG. 1
, conventional source erase operations for the flash memory cell
10
operate in the following manner. The memory cell
10
is programmed by applying a relatively high voltage V
G
(e.g., approximately 12 volts) to the control gate
28
and a moderately high voltage V
D
(e.g., approximately 9 volts) to the drain region
14
in order to produce “hot” electrons in the channel region
16
near the drain region
14
. The hot electrons accelerate across the tunnel oxide
22
and into the floating gate
24
and become trapped in the floating gate
24
since the floating gate
24
is surrounded by insulators (the interpoly dielectric
26
and the tunnel oxide
22
). As a result of the trapped electrons, the threshold voltage of the memory cell
10
increases by about 3 to 5 volts. This change in the threshold voltage (and thereby the channel conductance) of the memory cell
10
created by the trapped electrons causes the cell to be programmed.
To read the flash memory cell
10
, a predetermined voltage V
G
that is greater than the threshold voltage of an unprogrammed cell, but less than the threshold voltage of a programmed cell, is applied to the control gate
28
. If the memory cell
10
conducts, then the memory cell
10
has not been programmed (the cell
10
is therefore at a first logic state, e.g., a zero “0”). Likewise, if the memory cell
10
does not conduct, then the memory cell
10
has been programmed (the cell
10
is therefore at a second logic state, e.g., a one “1”). Consequently, it is possible to read each cell
10
to determine whether or not it has been programmed (and therefore identify its logic state).
In order to erase the flash memory cell
10
, a relatively high voltage V
S
(e.g., approximately 12 volts) is applied to the source region
12
and the control gate
28
is held at a ground potential (V
G
=0), while the drain region
14
is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide
22
between the floating gate
24
and the source region
12
. The electrons that are trapped in the floating gate
24
flow toward and cluster at the portion of the floating gate
24
overlying the source region
22
and are extracted from the floating gate
24
and into the source region
12
by way of Fowler-Nordheim tunneling through the tunnel oxide
22
. Consequently, as the electrons are removed from the floating gate
24
, the memory cell
10
is erased.
The ONO interpoly dielectric layer has a number of important functions including insulating the control gate from the floating gate. Accordingly, it is desirable to form a high quality, relatively thin ONO interpoly dielectric layer. When forming an ONO interpoly dielectric layer, there are a number of concerns. For example, if the top oxide layer is too thick, the required programming voltage increases undesirably. Precisely controlling the thickness of the top oxide layer is a notable concern.
When forming a conductive layer made of tungsten silicide over the polysilicon control gate, tungsten hexafluoride is typically employed. The fluorine content of a tungsten silicide layer made in a conventional manner is typically above about 2×10
20
atoms/cm
3
. However, when forming tungsten silicide from tungsten hexafluoride, fluorine undesirably diffuses into the top oxide of the ONO interpoly dielectric layer. The undesirable fluorine diffusion causes the top oxide to swell, often by at least about 10%, and even by at least about 20% in thickness. As stated above, an increase in the top oxide thickness requires an undesirable increase in the required programming voltage thus lowering the coupling ratio.
In this connection, there are a number of concerns when forming the conductive layer over the polysilicon control gate. For example, the conductive layer should adequately adhere to the polysilicon control gate. The inability of the conductive layer to adequately adhere to the polysilicon control gate is typically due to delamination of the conductive layer. The conductive layer should also effectively conduct an electrical current. However, current methods of forming a tungsten silicide conductive layer over the polysilicon control gate of a flash memory device result in deleterious microcracking within the tungsten silicide. This is sometimes due to poor step coverage when forming a tungsten silicide conductive layer. Microcracking leads often to undesirably increased word line resistance and poor polysilicon control gate performance.
In view of the aforementioned concerns and problems, there is a need for flash memory cells of improved quality and more efficient methods of making such memory cells.
SUMMARY OF THE INVENTION
As a result of the present invention, a flash memory cell having improved reliability is obtainable by providing an improved ONO int

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