Method of forming nitride capped Cu lines with reduced...

Details Method of forming nitride capped Cu lines with reduced... Method of forming nitride capped Cu lines with reduced...

2001-07-12

2002-08-06

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S627000, C438S628000, C438S629000, C438S643000, C438S644000, C438S653000, C438S654000, C438S678000

Reexamination Certificate

active

06429128

ABSTRACT:

TECHNICAL FIELD
The present invention relates to copper (Cu) and/or Cu alloy metallization in semiconductor devices, particularly to a method for forming reliably capped Cu or Cu alloy interconnects, such as single and dual damascene structures formed in low dielectric constant materials. The present invention is particularly applicable to manufacturing high speed integrated circuits having submicron design features and high conductivity interconnects with improved electromigration resistance.
BACKGROUND ART
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low R×C (resistance x capacitance) interconnect pattern with electromigration resistance, particularly wherein submicron vias, contacts and trenches have high aspect ratios imposed by miniaturization.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor “chips” comprising five or more levels of metallization are becoming more prevalent as device geometry's shrink to submicron levels.
A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric on a conductive layer comprising at least one conductive pattern, forming an opening through the interlayer dielectric by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the interlayer dielectric is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the interlayer dielectric and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. As the length of metal interconnects increases and cross-sectional areas and distances between interconnects decrease, the R×C delay caused by the interconnect wiring increases. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As design rules are reduced to about 0.12 micron and below, the rejection rate due to integrated circuit speed delays significantly reduces production throughput and increases manufacturing costs. Moreover, as line widths decrease electrical conductivity and electromigration resistance become increasingly important.
Cu and Cu alloys have received considerable attention as a candidate for replacing Al in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistively than Al. In addition, Cu has improved electrical properties vis-à-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring.
An approach to forming Cu plugs and wiring comprises the use of damascene structures employing CMP. However, due to Cu diffusion through interdielectric layer materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium (Ti), titanium-tungsten (TiW), tungsten (W), tungsten nitride (WN), Ti—TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
There are additional problems attendant upon conventional Cu interconnect methodology employing a diffusion barrier layer (capping layer). For example, conventional practices comprise forming a damascene opening in an interlayer dielectric, depositing a barrier layer such as TaN, lining the opening and on the surface of the interlayer dielectric, filling the opening with Cu or a Cu alloy layer, CMP, and forming a capping layer on the exposed surface of the Cu or Cu alloy. It was found, however, that capping layers, such as silicon nitride, deposited by plasma enhanced chemical vapor deposition (PECVD), exhibit poor adhesion to the Cu or Cu alloy surface. Consequently, the capping layer is vulnerable to removal, as by peeling due to scratching or stresses resulting from subsequent deposition of layers. As a result, the Cu or Cu alloy is not entirely encapsulated and Cu diffusion occurs, thereby adversely affecting device performance and decreasing the electromigration resistance of the Cu or Cu alloy interconnect member.
In copending application Ser. No. 09/497,850 filed on Feb. 4, 2000, a method is disclosed comprising treating the surface of a Cu or Cu alloy layer with a plasma containing nitrogen (N
2
) and ammonia (NH
3
), followed by depositing the capping layer in the presence of N
2
in the same reaction chamber for improved adhesion of the capping layer to the Cu or Cu alloy interconnect. This technique has been effective in improving adhesion of the capping layer. However, after further experimentation and investigation, it was found that capped Cu or Cu alloy interconnects, as in damascene and dual damascene structures, exhibited poor electromigration resistance, particular in those cases wherein the exposed surface of the Cu or Cu alloy was treated with a plasma to remove a copper oxide surface film prior to deposition of the capping layer, e.g., silicon nitride. Such poor electromigration resistance adversely impacts device reliability and results in poor product yield.
In copending application Ser. No. 09/846,186 filed on May 2, 2001 a method of plasma treating an upper surface of inlaid Cu or Cu alloy metallization is disclosed using a relatively soft NH
3
plasma treatment heavily diluted with N
2
, ramping up the introduction of silane (SiH
4
) and then initiating plasma enhanced chemical vapor deposition (PECVD) while maintaining the same pressure during plasma treatment, SiH
4
ramp up and silicon nitride capping layer deposition, with an attendant significant improvement in electromigration resistance, within wafer uniformity and wafer-to-wafer uniformity.
As design rules extend deeper into the submicron range, the reliability of interconnect patterns becomes particularly cr

Affiliated with

Also associated with

Rating

Method of forming nitride capped Cu lines with reduced... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming nitride capped Cu lines with reduced..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming nitride capped Cu lines with reduced... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2887686