Method of forming nanocrystals in a memory device

Details Method of forming nanocrystals in a memory device Method of forming nanocrystals in a memory device

2002-08-30

2004-10-26

Chen, Jack (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S260000, C438S503000

Reexamination Certificate

active

06808986

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to the field of semiconductors and more specifically to memory devices.
BACKGROUND OF THE INVENTION
Electrically erasable programmable read only memory (EEPROM) structures are commonly used in integrated circuits for non-volatile date storage. EEPROM device structures commonly include a polysilicon floating gate formed over a tunnel dielectric, which is formed over a semiconductor substrate, to store charge. As device dimensions and power supply voltages decrease, the thickness of the tunnel dielectric cannot correspondingly decrease in order to prevent data retention failures. An EEPROM device using isolated silicon nanocrystals as a replacement to the floating gate does not have the same vulnerability to isolated defects in the tunnel dielectric and thus, permits scaling of the tunnel dielectric and the operating voltage without compromising data retention.
In order to have a significant memory effect as measured by the threshold voltage shift of the EEPROM device, it is necessary to have a high density of silicon nanocrystals of approximately 1E12 nanocrystals per cm
2
. One method to achieve such a density of nanocrystals is to fabricate the nanocrystals using ultra high vacuum chemical vapor deposition (UHVCVD) using disilane (Si
2
H
6
). However, the length of the process time is greater than 10 minutes per wafer, which results in undesirable increased cycle time and manufacturing costs. Other approaches to form nanocrystals on the tunnel dielectric have resulted in achieving densities significantly less than desired (e.g., 5E11 nanocrystals per cm
2
). Therefore, a need exists to form nanocrystals at desired densities without increasing manufacturing cycle time or cost.


REFERENCES:
patent: 5830538 (1998-11-01), Gates et al.
patent: 5850064 (1998-12-01), Goldstein
patent: 6060743 (2000-05-01), Sugiyama et al.
patent: 6090666 (2000-07-01), Ueda et al.
patent: 6268041 (2001-07-01), Goldstein
patent: 6297095 (2001-10-01), Muralidhar et al.
patent: 6344403 (2002-02-01), Madhukar et al.
patent: 6455372 (2002-09-01), Weimer
Fernandes et al, “Memory Characteristics of Si Quantum Dot Devices with SiO2/ALD AI2O3Tunneling Dielectrics,” Electron Devices Meeting, 2001, IEDM TEchnical Digest. International, 2001, pp. 74.1-74.4.
Baron et al., “Growth by Low Pressure Chemical Vapor Deposition of Silicon Quantum Dots on Insulator for Nanoelectronics Devices,” Materials Research Society Sumposium Proc. vol. 571, 2000 Materials Research Society, pp. 37-42.
Madhukar et al., “CVD Growth of Si Nanocrystals on Dielectric Surfaces for Nanocrystal Floating Gate Memory Application,” Materials Research Society Proc. vol. 638, 2001 Materials Research Society, pp. F5.2.1-F5.3.1.
Kamins, “Polycrystalline Silicon for Integrated Circuits and Displays,” 2nd Edition, Kluwer Academic Publishers, 1998, Boston, p. 44.
Kawashima et al., “Monitoring of Silicon Nano-Crystal Formation on SiO2and on Si3N4in an UHV-CVD System,” Presented at the Materials Research Society 2001 Fall Meeting in the Symposium on Nanoparticulate Materials, Boston, MA, 7 pgs, without Abstract Section.
De Blauwe et al., “A Novel, Aerosol-Nanocrystal Floating-Gate Device for Non-Volatile Memory Applications,” Electron Devices Meeting 2000, IEDM Technical Digest. International, pp. 683-686.
Hu et al., “Real Time Investigation of Nucleation and Growth of Silicon on Silicon Dioxide Using Silane and Disilane in a Rapid Thermal Processing System,” J. Vac. Sci. Technol. B 14(2), Mar./Aug. 1996, pp. 744-750.
Leach et al., “Cracking Assisted Nucleation in Chemical Vapor Deposition on Silicon Dioxide,” Journal of Crystal Growth, vol. 240, No. 3-4, pp. 415-422 (2002).
Masato Oishi et al,“Fabrication of Silicon Nano-Crystal Dots on SiO2by Ultrahigh-Vacuum Chemical Vapor Deposition,” Materials Research Society, Symposium Procedures, vol. 638, 3 pgs. (2001).
F. Mazen et al., “Control of Silicon Quantum Dots Nucleation and Growth by CVC,” Materials Research Society, Symposium Procedures, vol. 737, pp. F1.9.1-F1.9.6 (2003).
Quin et al., “Observation of Coulomb-Blockade in a Field-Effect Transistor With Silicon Nanocrystal Floating Gate at Room Temperature,” Solid State Communications 111, 1999, pp. 171-174.
PCT/US03/16289 International Search Report.

Affiliated with

Also associated with

Rating

Method of forming nanocrystals in a memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming nanocrystals in a memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming nanocrystals in a memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3302072