Method of forming multiple wells in a semiconductor...

Details Method of forming multiple wells in a semiconductor... Method of forming multiple wells in a semiconductor...

1999-05-21

2001-08-07

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S526000, C438S519000, C438S527000

Reexamination Certificate

active

06271105

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 8-22393, filed on Jun. 15, 1998, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a well of a semiconductor integrated circuit, and more particularly, to a method for forming a multiple well.
A low power semiconductor integrated circuit generally includes MOS transistors. A MOS transistor may be an NMOS transistor or a PMOS transistor, and a CMOS circuit including both NMOS transistors and PMOS transistors has the lowest power consumption of currently-available integrated circuits. So, if a CMOS circuit is employed for a semiconductor integrated circuit, NMOS transistors and PMOS transistors are both formed on a single substrate.
Generally NMOS transistors are formed in P-well regions, and PMOS transistors are formed in N-well regions. Furthermore, in order to apply various back biases to a plurality of NMOS transistors constituting the semiconductor integrated circuit, e.g, two NMOS transistors, the two NMOS transistors must be formed in P-well regions which are isolated from each other. Furthermore, if the semiconductor substrate is p-type, any P-well regions formed directly in the p-type substrate will be electrically connected to each other through the semiconductor substrate. Thus, at least one of the two P-well regions must be surrounded by a well region having a conductivity type different from that of the semiconductor substrate, e.g., an N-well region. Such technology for forming a pocket P-well region in the p-type semiconductor substrate, surrounded with an N-well region, a P-well region directly formed on the p-type semiconductor substrate, and an N-well region directly formed in the p-type semiconductor substrate is called triple well technology.
If cell transistors constituting the cell array region of a semiconductor memory are formed in a pocket P-well region formed by the triple well technology, a soft error rate (SER) due to alpha particles can be reduced. Accordingly, the triple well technology is widely employed for the most highly integrated semiconductor memories.
In
FIGS. 1 through 4
, reference characters “a” and “b” denote a cell array region and a peripheral circuit region, respectively.
Referring to
FIG. 1
, a first photoresist pattern
3
, exposing a cell array region a, is formed over a semiconductor substrate
1
, e.g., a p-type semiconductor substrate. Subsequently, a first ion implantation process I
1
, for implanting an n-type impurity into the semiconductor substrate
1
, is performed using the first photoresist pattern
3
as an ion implantation mask. This forms a deep N-well region
5
to a predetermined depth from the surface of the semiconductor substrate
1
.
Referring to
FIG. 2
, the first photoresist pattern
3
is removed, and a second photoresist pattern
7
exposing the cell array region a is formed. However, the region exposed by the second photoresist pattern
7
is narrower than that exposed by the first photoresist pattern
3
. A second ion implantation process I
2
for implanting a p-type impurity into the surface of the semiconductor substrate
1
is performed using the second photoresist pattern
7
as an ion implantation mask. This forms a pocket P-well region
9
above the deep N-well region
5
. The pocket P-well region
9
is narrower than that of the deep N-well region
5
, as shown in FIG.
2
. After performing the second ion implantation process I
2
, an ion implantation process for optimizing the characteristics of a cell transistor, e.g., an ion implantation process for controlling a threshold voltage, is then performed on the surface of the pocket P-well region
9
, using the second photoresist pattern
7
.
Referring to
FIG. 3
, the second photoresist pattern
7
is removed, and a third photoresist pattern
11
partially exposing the peripheral circuit region b is formed. A third ion implantation process I
3
for implanting a p-type impurity into the surface of the semiconductor substrate
1
is performed using the third photoresist pattern
11
as an ion implantation mask. This forms a P-well region
13
in a predetermined area of the peripheral circuit region b. After the third ion implantation process I
3
, an ion implantation process for optimizing the characteristics of an NMOS transistor of a peripheral circuit, e.g., an ion implantation process for controlling a threshold voltage, is then performed on the surface of the P-well region
13
, using the third photoresist pattern
11
as an ion implantation mask.
Referring to
FIG. 4
, the third photoresist pattern
11
is removed, and a fourth photoresist pattern
15
covering the pocket P-well region
9
and the P-well region
13
is formed. A fourth ion implantation process I
4
for implanting an n-type impurity into the surface of the semiconductor substrate
1
is performed using the fourth photoresist pattern
15
as an ion implantation mask. This forms an N-well region
17
in the peripheral circuit region b.
Subsequently, the semiconductor substrate is annealed to activate the impurities implanted into the ion implantation regions. The N-well region
17
is connected to the edges of the deep N-well region
5
formed in the cell array region a, as shown in FIG.
4
. Thus, the pocket P-well region
9
is completely isolated from the semiconductor substrate
1
by the deep N-well region
5
and the N-well region
17
of the peripheral circuit region b.
In the conventional art, four photolithography processes are required to form a triple well. Also, if misalignment occurs between the first photoresist patten for defining the deep N-well region and the second photoresist pattern for defining the pocket P-well region, the pocket P-well region is not completely isolated from the semiconductor substrate. Thus, in order to increase a process margin with respect to the misalignment, a well design rule must be increased. However, if the well design rule is increased, the size of individual elements cannot be easily reduced and it becomes difficult to increase the integration of the semiconductor device.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a method for forming a multiple well of a semiconductor device, requiring fewer photolithography processes, to simplify the manufacturing process, and allowing a reduced a well design rule.
Accordingly, to achieve the above objective, in the present invention, a first ion implantation mask is formed over a semiconductor substrate of a first conductivity type, e.g., p-type, exposing a predetermined first region of the semiconductor substrate.
A first deep well region of a second conductivity type is formed by performing a first ion implantation process for implanting an impurity of a second conductivity type, e.g., n-type, into the first region of the semiconductor substrate, exposed by the first ion-implantation mask. The first deep well region of the second conductivity type is formed to a predetermined depth from the surface of the semiconductor substrate. Subsequently, a pocket well region of the first conductivity type is formed over the first deep well region by performing a second ion implantation process for implanting an impurity of a first conductivity type into the first region of the semiconductor substrate exposed by the first ion-implantation mask.
The first and second ion implantation processes may be performed in either order. The pocket well region may be formed first, then the first deep well region formed second, or the first deep well region can be formed first and the pocket well region formed second.
The first ion-implantation mask is then removed, and a second ion-implantation mask exposing a predetermined second region of the semiconductor substrate apart from the pocket well region is formed. A first peripheral well region of the first conductivity type is formed by performing a third ion implantation process for implanting an impurity of the first conductivity type into the second

Affiliated with

Also associated with

Rating

Method of forming multiple wells in a semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming multiple wells in a semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming multiple wells in a semiconductor... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2523052