Method of forming mosfets with recessed self-aligned silicide gr

Details Method of forming mosfets with recessed self-aligned silicide gr Method of forming mosfets with recessed self-aligned silicide gr

1998-01-05

1999-10-26

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438524, 438636, 438655, H01L 21336

Patent

active

059727624

ABSTRACT:
A gate oxide layer is formed on the substrate. A polysilicon layer is deposited on the gate oxide layer. Then, a ARC layer is deposited on the polysilicon layer. Next, etching is used to etch the ARC layer, polysilicon layer for forming a gate structure. An ion implantation is carried out to form lightly doped drain (LDD). Subsequently, a silicon nitride layer is formed along the surface of substrate, and the gate structure. Then, side wall spacers are formed on the side walls of the gate structure. The silicon substrate is slightly recessed to generate recess portions under a portion of the side wall spacers. Then, an ion implantation is performed to form source and drain (S/D). Then, the silicon nitride layer formed on the gate and the side wall spacers are removed. Subsequently, the gate oxide is etched to form undercut portions under the gate. Subsequently, a silicon oxynitride layer is formed on the substrate, and the gate structure. Side wall spacers are formed on the side walls of the gate structure. Self-aligned silicide (SALICIDE) layer, polycide layer are respectively formed on the S/D, and on the polysilicon gate.

REFERENCES:
patent: 4963502 (1990-10-01), Teng et al.
patent: 5382534 (1995-01-01), Sheu et al.
patent: 5491099 (1996-02-01), Hsu
patent: 5798291 (1998-08-01), Lee et al.

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