Method of forming MOS transistor

Details Method of forming MOS transistor Method of forming MOS transistor

2005-03-22

2005-03-22

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000

Reexamination Certificate

active

06869835

ABSTRACT:
Methods of simultaneously forming MOS transistors and a capacitor on a substrate having gate insulation layers of varying thicknesses. A method includes forming field regions in a substrate to define a first transistor region, a capacitor region, and a second transistor region, forming a first gate stack in the first transistor region and a lower electrode in the capacitor region, and forming an upper electrode on the lower electrode with a dielectric layer interposed therebetween and a second gate stack in the second transistor region.

REFERENCES:
patent: 5449629 (1995-09-01), Kajita
patent: 5497018 (1996-03-01), Kajita
patent: 6238967 (2001-05-01), Shiho et al.
patent: 6303455 (2001-10-01), Hou et al.
patent: 6391755 (2002-05-01), Ma et al.

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