Method of forming MOS/CMOS devices with dual or triple gate...

Details Method of forming MOS/CMOS devices with dual or triple gate... Method of forming MOS/CMOS devices with dual or triple gate...

2000-07-12

2001-07-31

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S981000

Reexamination Certificate

active

06268251

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to methods of forming semiconductor devices and specifically to methods of forming metal-oxide-semiconductor (MOS) and complimentary-metal-oxide-semiconductor (CMOS) devices with varying thicknesses of gate oxides.
BACKGROUND OF THE INVENTION
Thick gate oxide quality is adversely affected when another, thinner gate oxide is formed from a portion of the thick oxide by partially removing that portion of the thick gate oxide and by a subsequent cleaning process. Additionally, thick gate oxide integrity (GOI) failure will occur.
Further, there is not available a reliable method of forming triple gate oxides, each with a different thickness, in MOS/CMOS devices on the same wafer.
A method of forming such triple, or greater, gate oxides on the same wafer will have potential application when device dimensions, or design rule, becomes smaller and smaller which may well require different operating voltages for the input and output of transistors. The lower the voltage, the thinner the gate oxide. The gate oxide of a lower voltage device, i.e. having a thinner gate oxide, cannot withstand the higher voltage of an older technology device and will wear out, or fail, too quickly.
U.S. Pat. No. 5,926,708 to Martin describes a method of manufacturing an integrated circuit with two or more gate oxide thicknesses on the same wafer. A first gate oxide layer is formed on a semiconductor wafer. A first layer of polysilicon is formed over the first gate oxide layer and a polish stop film is formed over the first polysilicon layer. The polish stop and first poly layer are etched to expose a portion of the first gate oxide layer. The exposed first gate layer portion is stripped to expose a portion of the underlying wafer. A second gate oxide layer, thicker than the first gate oxide layer, is then formed on the exposed wafer portion and a gate conductor material layer is formed over the second gate oxide layer, blanket covering the first poly layer. The gate conductor layer is planarized by CMP to remove it form the first poly layer, forming a gate conductor.
U.S. Pat. No. 5,953,599 to El-Diwany describes a method of forming a thin layer of gate oxide for low-voltage transistors that support the logic operations of a CMOS device, and a thick layer of gate oxide for high-voltage transistors that support the analog operations of the device.
U.S. Pat. No. 5,432,114 to O describes a method of fabricating an IGFET integrated circuit (IC) having two gate dielectric layers with different parameters. The O process is typically used for fabrication of dual voltage CMOS integrated circuits. The IC may include high voltage transistors having a first gate dielectric thickness and low voltage transistors having a second gate dielectric thickness.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of forming MOS/CMOS devices having dual, i.e. both thick and thin, quality gate oxides.
Another object of the present invention is to provide a method of forming MOS/CMOS devices having dual, i.e. both thick and thin, quality gate oxides while maintaining gate oxide integrity (GOI).
A further object of the present invention is to provide a method of forming MOS/CMOS devices having triple, i.e. thick, intermediate, and thin, quality gate oxides.
Yet another object of the present invention is to provide a method of forming MOS/CMOS devices having triple, i.e. thick, intermediate, and thin, quality gate oxides while minimizing the gate oxide integrity (GOI) issue.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a silicon substrate having at least a first and second gate oxide region is provided. A first gate oxide layer is formed over the silicon substrate within the first gate oxide region. The first gate oxide layer having a first predetermined thickness. A first layer of polysilicon is deposited and planarized over the first gate oxide layer. The first planarized layer of polysilicon and the first gate oxide layer are masked and etched within the second gate oxide region, exposing the silicon substrate within the second gate oxide region. A second gate oxide layer is formed over the exposed silicon substrate within the second gate oxide region. The second gate oxide layer having a second predetermined thickness. A second layer of polysilicon is selectively deposited over the second gate oxide layer. The first and second layers of polysilicon are planarized to a uniform thickness. Whereby the second gate oxide layer predetermined thickness is less than the first gate oxide layer predetermined thickness.


REFERENCES:
patent: 5432114 (1995-07-01), O
patent: 5595922 (1997-01-01), Tigelaar et al.
patent: 5926708 (1999-07-01), Martin
patent: 5926729 (1999-07-01), Tsai et al.
patent: 5953599 (1999-09-01), El-Diwany
patent: 5970345 (1999-10-01), Hattangady et al.
patent: 2-237037 (1990-09-01), None

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