Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2009-05-06
2010-10-19
Chen, Jack (Department: 2893)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S717000, C438S723000, C438S734000, C257SE21023
Reexamination Certificate
active
07816270
ABSTRACT:
A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.
REFERENCES:
patent: 7202174 (2007-04-01), Jung et al.
patent: 7550391 (2009-06-01), Jeon et al.
patent: 7687369 (2010-03-01), Koh et al.
patent: 2006/0240361 (2006-10-01), Lee et al.
patent: 10-2006-0110706 (2006-10-01), None
patent: 10-0672123 (2007-01-01), None
patent: 10-0746618 (2007-07-01), None
Park Jae-kwan
Park Sang-yong
Sim Jae-hwang
Yim Yong-sik
Chen Jack
Lee & Morse P.C.
Samsung Electronics Co,. Ltd.
LandOfFree
Method of forming minute patterns in semiconductor device... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming minute patterns in semiconductor device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming minute patterns in semiconductor device... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4242063