Method of forming MIM capacitor

Details Method of forming MIM capacitor Method of forming MIM capacitor

2001-07-02

2002-05-14

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000

Reexamination Certificate

active

06387750

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a metal-insulator-metal capacitor, and more particularly to a method of forming a metal-insulator-metal capacitor having a three dimensional structure.
2. Description of the Related Art
Capacitor structures for semiconductor integrated circuits include metal-oxide-semiconductor (MOS) capacitors, PN junction capacitors, and polysilicon-insulator-polysilicon (PIP) capacitors. Each of these capacitor structures includes at least one monocrystalline silicon layer or polycrystalline silicon layer which is used as a capacitor electrode. The use of silicon for the capacitor electrode, however, may result in a higher electrode resistance than is desired.
It is thus desirable to reduce the resistance of capacitor electrodes to decrease frequency dependence of the capacitor. Accordingly, metal-insulator-metal (MIM) thin film capacitors have been developed to provide low electrode resistances. Moreover, metal-insulator-metal capacitors can be used in integrated circuits requiring high speed performance. In addition, metal-insulator-metal thin film capacitors have been applied to advanced analog semiconductor devices because these capacitors have capacitance fluctuation rates dependent on voltage and temperature which are sufficiently low to provide desirable electrical characteristics.
In addition, there have been efforts to reduce thicknesses of dielectric layers for integrated circuit capacitors to thereby increase the performance of capacitors including these thinner dielectric layers. In particular, the capacitance of a capacitor can be increased by reducing the thickness of the dielectric layer between the two electrodes of the capacitor. There have also been efforts to increase capacitances by using dielectric layers having relatively high dielectric constants, and by increasing the surface areas of the capacitor electrodes. Furthermore, multi-wiring or multilevel interconnect processes have been applied to semiconductor manufacturing methods to facilitate the development of high-density integration and microelectronic technology. Accordingly, metal-insulator-metal thin film capacitors can be manufactured together with multi-wiring structures.
FIG. 1
shows a cross-sectional diagram of a conventional metal-insulator-metal capacitor. The metal-insulator-metal capacitor comprising a lower aluminum electrode
102
, an insulating layer
106
and an upper aluminum electrode
108
is formed on a substrate
100
. A dielectric layer
110
and a titanium nitride layer
104
are also shown in this figure. In view of the demands of high integration and large capacitance, the conventional planar MIM capacitor shown in
FIG. 1
will not meet the requirement of modern integrated circuits gradually. Thus it is very necessary to provide a novel process of forming MIM capacitors which can provide a new structure of the MIM capacitors having large capacitance as well as high integration of the integrated circuit. It is toward these goals that this invention specially directs.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a process of forming a three dimensional MIM capacitor.
It is another object of this invention to provide a MIM capacitor having a three dimensional structure and an upgraded capacitance.
It is a further object of this invention to provide a three dimensional MIM capacitor which can effectively upgrade the integration of integrated circuits.
To achieve these objects, and in accordance with the purpose of the invention, the invention uses a method comprising: providing a substrate having a first region and a second region; forming a first conductive layer over said substrate and a second conductive layer over said first conductive layer; transferring a plurality of trench patterns into said second conductive layer and said first conductive layer to form a plurality of trenches in said first region and said second region; conformally forming a dielectric layer over said second conductive layer and said first conductive layer; forming a third conductive layer over said dielectric layer; forming a photoresist layer to cover said first region; removing said third conductive layer on said second region to expose said dielectric layer on said second region; removing said dielectric layer on said second region to expose said second conductive layer and said first conductive layer on said second region; etching through the bottoms of said trenches in said second region to expose said substrate; and removing said photoresist layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5918135 (1999-06-01), Lee et al.
patent: 6259128 (2001-07-01), Adler et al.

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