Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-11-14
2010-11-02
Le, Thao (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21248
Reexamination Certificate
active
07824994
ABSTRACT:
Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.
REFERENCES:
patent: 5994210 (1999-11-01), Kerr
patent: 6074915 (2000-06-01), Chen et al.
patent: 6157056 (2000-12-01), Takeuchi et al.
patent: 6191975 (2001-02-01), Shimizu et al.
patent: 6492690 (2002-12-01), Ueno et al.
patent: 6521527 (2003-02-01), Kuroi et al.
patent: 6703669 (2004-03-01), Goda et al.
patent: 6828627 (2004-12-01), Goda et al.
patent: 6900086 (2005-05-01), Mori et al.
patent: 6967892 (2005-11-01), Tanaka et al.
patent: 2002/0113257 (2002-08-01), Osabe et al.
patent: 2004/0166596 (2004-08-01), Sashida et al.
patent: 2004/0188774 (2004-09-01), Takeda et al.
patent: 2005/0133831 (2005-06-01), Cheng et al.
patent: 2005/0227440 (2005-10-01), Ema et al.
patent: 2005/0243601 (2005-11-01), Harari
patent: 2005/0277251 (2005-12-01), Lee et al.
patent: 2005/0280000 (2005-12-01), Ishii et al.
patent: 2006/0118847 (2006-06-01), Takamatsu et al.
patent: 2006/0118855 (2006-06-01), Lee et al.
patent: 2006/0121685 (2006-06-01), Izumi
patent: 2006/0151821 (2006-07-01), Melik-Martirosian et al.
patent: 2006/0175642 (2006-08-01), Dote et al.
patent: 2006/0234455 (2006-10-01), Chen et al.
patent: 2007/0166912 (2007-07-01), Fenigstein et al.
patent: 2007/0238234 (2007-10-01), Wang et al.
Hook et al., “The Effects of Fluorine on Parametrics and Reliability in a 0.18-um 3.5/6.8nm Dual Gate Oxide CMOS Technology,” IEEE Transactions on Electron Devices, 48:1346-53, 2001.
Nguyen et al., “Effects of Fluorine Implants on Induced Charge Components in Gate-Oxides Under Constant-Current Fowler-Nordheim Stress,” IEEE Transactions on Electron Devices, 44:1432-40, 1997.
Nishioka et al., “Dramatic Improvement of Hot-Electron-Induced Interface Degradation in MOS Structures Containing F or Cl in SiO2”, IEEE Electron Letters, 9:38-40, 1988.
Wright et al., “The Effect of Fluorine on Gate Dielectric Properties”, IEDM 574-577, 1987.
Aritome Seiichi
Larsen Chris
Li Di
Moradi Behnam
Prall Kirk
Le Thao
Micro)n Technology, Inc.
Wells St. John P.S.
LandOfFree
Method of forming memory devices by performing halogen ion... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming memory devices by performing halogen ion..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming memory devices by performing halogen ion... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4183502