Method of forming memory device having capacitor including...

Details Method of forming memory device having capacitor including... Method of forming memory device having capacitor including...

2002-04-03

2003-11-04

Le, D (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S675000, C438S435000, C438S639000, C257S306000, C257S295000

Reexamination Certificate

active

06642144

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a memory device having a capacitor with a high dielectric constant layer in a ferroelectric random access memory (FRAM). More particularly, the present invention relates to a method of fabricating an alignment key that maintains its integrity during a step of crystallizing a high dielectric constant layer on a substrate during the formation a memory device having a capacitor with a high dielectric constant layer.
2. Description of the Related Art
As semiconductor devices become highly integrated, a memory device having a capacitor is required to include a capacitor having a small formation area and a large capacitance value. In a conventional method of realizing a capacitor having a small formation area and a large capacitance value, a dielectric layer having a high dielectric constant is used. Particularly, a method of forming a nonvolatile memory, which does not require a refresh function and has a high operation characteristic, has been recently studied wherein a ferroelectric material is used as a high dielectric constant material.
Representative high dielectric constant materials are metal compounds of a titanic acid such as PZT and BST. In order that these compounds may have a high dielectric constant, or ferroelectricity, a crystallization should be performed on an amorphous structure that is easily formed and treated on a substrate. Alternatively, another crystallization having a ferroelectric property should be performed. For the conventional crystallization of these materials, the materials require treatment at a high temperature, under an oxygen ambient, for a certain time. When these materials are treated under an oxygen ambient at a high temperature, a problem occurs in that a previously formed part of a semiconductor device is influenced by the process condition.
For example, a storage node contact hole is formed at an interlayer insulation layer and filled with polysilicon to form a contact plug. Conductors, which are not easily oxidized, such as platinum and iridium, are formed on the contact plug as a capacitor bottom electrode. A high dielectric constant layer is then formed on the bottom electrode and crystallization is performed under an oxygen ambient at a high temperature. At this time, even if the polysilicon contact plug is covered with layers of platinum and the like, these layers may not function as oxygen barriers effectively. Thus, when annealing is performed at a high temperature, a top of the contact plug is easily oxidized. When the top of the contact plug is oxidized, the top of the contact plug becomes a nonconductor, so that the resistance of the contact is increased and a problem occurs in the operation of the capacitor device.
FIG.
1
through
FIG. 3
illustrate cross-sectional views of a conventional embodiment that induces a problem during the crystallization of a high dielectric constant layer material. In this conventional embodiment, in order to increase conductivity of a contact plug, tungsten is used instead of polysilicon.
Referring to
FIG. 1
, a transistor structure including a gate electrode
13
is formed on a substrate
10
at a cell region.
Additionally, a first interlayer insulation layer
15
, a bit line
17
, a bit line contact
20
and a second interlayer insulation layer
19
are formed. A storage node contact hole
21
is formed in interlayer insulation layers
15
and
19
, and the contact hole is filled with a tungsten layer
23
by a tungsten chemical vapor deposition (CVD).
At this time, an alignment key is formed at a scribe line or a peripheral region of a chip for use in a subsequent pattern alignment process. The alignment key is made by forming a relatively wide window or a groove
24
by etching the interlayer insulation layer
19
concurrent with the formation of the storage node contact hole
21
. Thus, when the tungsten CVD is performed, the tungsten layer
23
fills the narrow storage node contact hole
21
to form a plug. Additionally, the tungsten layer
23
is conformally stacked on the inner sidewalls of the groove
24
forming the alignment key, and the width of the groove
24
narrows.
Referring to
FIG. 2
, a chemical mechanical polishing (CMP) process is performed with respect to the tungsten at the cell region so that the tungsten layer above the second interlayer insulation layer
19
is removed and only a storage node contact plug
231
remains. An iridium/iridium oxide layer
25
and a platinum layer
27
are then stacked as a bottom electrode, and BST((Ba,Sr)TiO
3
) or PZT(Pb(Zr,Ti)O
3
) is stacked as a high dielectric constant layer
29
. At this time, except for a residual tungsten layer
233
on the inner surface of the groove forming the alignment key, the tungsten layer is removed by the CMP process. The iridium/iridium oxide layer
25
, the platinum layer
27
, and the high dielectric constant layer
29
, such as BST((Ba,Sr)TiO
3
) or PZT(Pb(Zr,Ti)O
3
), are conformally stacked according to an undulation formed by the groove at the substrate.
Referring to FIG.
2
and
FIG. 3
, the substrate of the
FIG. 2
is thermally treated under an oxygen ambient at a temperature of 700° C. The thermal treatment forms a crystallized high dielectric constant layer
291
. In the cell region, some oxygen may diffuse through the bottom electrode at the top of the tungsten layer forming the contact plug
231
. Diffusion of oxygen, however, is limited due to the presence of other layers
25
,
27
and
29
on the contact plug
231
and the narrow width of contact plug in comparison with the formation depth of the contact plug
231
. Accordingly, no significant problem in the conductivity of the contact plug
231
occurs. At the groove where the alignment key is formed, however, the residual tungsten layer
233
formed in the groove and covering the inner surface of the groove is contacted with the oxygen ambient through a wide area, so there is significant oxygen inflow. Thus, the tungsten is oxidized at a groove
235
forming the alignment key, which causes the tungsten to expand in volume. As a result, the groove is filled with a tungsten oxide layer, a lifted bottom electrode layer and a crystallized high dielectric constant layer
291
, such as a PZT layer. Consequently, selectivity of the alignment key is decreased, and in the case of aligning a substrate for patterning the crystallized high dielectric constant layer
291
and the bottom electrode in a subsequent process, it is difficult to fit the alignment key and an overlay key of a mask.
SUMMARY OF THE INVENTION
An advantage of the present invention is the capability to overcome a problem of sustaining an alignment key formed in a method of fabricating a semiconductor device including a process of crystallizing a ferroelectric layer or other high dielectric constant layer under an oxygen ambient at a high temperature.
It is a feature of an embodiment of the present invention to provide a method of forming a memory device capable of preventing the oxidation and expansion of a conductive layer covering an inner sidewall of a groove during a high dielectric constant layer crystallization process, which may occur even if the groove for an alignment key, which is formed in an interlayer insulation layer during the formation of a contact hole, is covered with a conductive layer of tungsten used during the formation of a contact plug.
Another feature of an embodiment of the present invention provides a method of forming a memory device having an alignment key in which no problems occur during crystallization of a high dielectric constant layer, even when a conductive layer of tungsten is used as a material for a contact plug for a capacitor bottom electrode.
Still another feature of an embodiment of the present invention provides a method wherein a groove for an alignment key is formed concurrently with a contact hole at a substrate; a conductive layer, such as a tungsten layer, is formed to fill the contact hole and cover the inner surface of

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