Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-04-21
2004-04-06
Ho, Hoai (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000, C438S211000, C438S261000, C365S185100
Reexamination Certificate
active
06716700
ABSTRACT:
BACKGROUND OF THE INVENTION
There are many examples of floating gate digital memories, whereby the threshold voltage of the floating gate transistors is changed by significant amounts, in the order of a few volts. One logic state is represented by a wide range of thresholds and the other logic state(s) is represented by a different range(s) of thresholds. Information is read from the cell generally by determining whether the transistor conducts or does not conduct when the transistor is biased into a predetermined read condition.
Analog storage, on the other hand, requires that small or continuous changes be made to the threshold of the floating gate transistor, and requires that the reading of the transistor give a determination of an actual voltage from the transistor, or an indication of how conductive the transistor is. Examples of analog storage can be found in U.S. Pat. No. 4,627,027 (Rai), U.S. Pat. No. 4,890,259 (Simko), U.S. Pat. No. 4,989,179 (Simko), U.S. Pat. No. 5,220,531 (Blyth), U.S. Pat. No.5,241,494 (Blyth), U.S. Pat. No. 5,294,819 (Simko), and U.S. Pat. No. 5,973,956 (Blyth).
The present invention provides a means by which an analog storage array configuration and a digital storage array configuration are produced from the same cell technology.
SUMMARY OF THE INVENTION
In accordance with yet another embodiment of the present invention, a method of manufacturing a first and second semiconductor memory array configurations wherein each array configuration includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal, includes the acts of: forming a plurality of rows of continuous program gate lines, each row of program gate line forming the program gate terminals of the cells along the row, the program gate lines being from a second layer polysilicon; forming a plurality of rows of continuous select gate lines, each row of select gate line forming the select gate terminals of the cells along the row, the select gate lines being from a third layer polysilicon; forming a plurality of rows of continuous source lines, each source line forming the source regions of the cells along the row, the source lines being from diffusion; wherein the first array configuration is obtained by: forming a plurality of local bitlines, the cells along each column being divided into a predesignated number of groups, the drain regions of the cells in each group being connected to one of the local bitlines extending across the cells in the group of cells; and forming a plurality of global bitlines along every two columns of cells, each global bitline being configured to selectively provide electrical connection to the local bitlines along the two columns of cells, wherein the local bitlines are from a first layer metal and the global bitlines are from a second layer metal.
In another embodiment, the second array configuration is obtained by forming a plurality of bitlines, the drain regions of the cells along each column being connected to one of the plurality of bitline, the bitlines being from a first layer metal.
In another embodiment, the first array configuration the cells coupled to a row of local bitlines form a segment block, and the method further includes: forming a first plurality of interconnect lines in each segment block, each of the first plurality of interconnect lines electrically connecting together the source lines within each segment block; and forming a second plurality of interconnect lines in each segment block, each of the second plurality of interconnect lines electrically connecting the program gate lines within each segment block, wherein the first and second plurality of interconnect lines are from first layer metal.
In another embodiment, the method further includes: forming a first horizontally extending interconnect line in each segment block, the first interconnect line electrically connecting the first plurality of interconnect lines; and forming a second horizontally extending interconnect line in each segment block, the second interconnect line electrically connecting the second plurality of interconnect lines together, wherein the first and second horizontally extending interconnect lines are from first layer metal.
In another embodiment, the method further includes forming first and second rows of segment select transistors in each segment block, the first row of segment select transistors providing electrical connection between the global bitlines and one half of the local bitlines in the segment block when selected, and the second row of segment select transistors providing electrical connection between the global bitlines and the remaining half of the local bitlines in the segment block when selected.
Further features and advantages of the present invention will become, more fully apparent from the following detailed description of the invention, the appended claims, and the accompanying drawings.
REFERENCES:
patent: 4627027 (1986-12-01), Rai et al.
patent: 4890259 (1989-12-01), Simko
patent: 4989179 (1991-01-01), Simko
patent: 5241494 (1993-04-01), Blyth et al.
patent: 5220531 (1993-06-01), Blyth et al.
patent: 5294819 (1994-03-01), Simko
patent: 5712180 (1998-01-01), Guterman et al.
patent: 5969987 (1999-10-01), Blyth et al.
patent: 5973956 (1999-10-01), Blyth et al.
patent: 2001/0014503 (2001-08-01), Iguchi et al.
Chang Ming-Bing
Kordesch Albert
Liu Chun-Mai
Ho Hoai
Townsend and Townsend / and Crew LLP
Tran Long
Windbond Electronics Corporation
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