Method of forming in-situ SRO HDP-CVD barrier film

Details Method of forming in-situ SRO HDP-CVD barrier film Method of forming in-situ SRO HDP-CVD barrier film

2003-03-27

2004-07-06

Cuneo, Kamand (Department: 2829)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C118S72300R, C257S760000, C438S783000, C438S787000, C438S788000

Reexamination Certificate

active

06759347

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to HDP-CVD deposition processes and more particularly to a method for forming a silicon-rich oxide (SRO) barrier film in-situ prior to forming a fluorosilicate glass (FSG) layer to avoid fluorine and plasma induced defects to a metallization layer.
BACKGROUND OF THE INVENTION
As devices become smaller and integration density increases, the high density plasma chemical vapor deposition (HDP-CVD) process has become, a key process due to its gap-filling capability. In particular, high density plasma (HDP) processes, such as electron cyclotron resonance (ECR) processes and induced coupling plasma (ICP) processes have been found to produce high-quality silicon dioxide and silicon nitride layers. Generally, HDP-CVD provides a high density of low energy ions resulting in higher quality films at lower deposition temperatures, compared to for example, PECVD. HDP-CVD is particularly ideal for forming interlayer dielectric (ILD) oxide layers because of its superior gap filling capability. Generally, both sputtering and deposition take place simultaneously, resulting in a deposition/sputter ratio (D/S/) ratio that may be adjusted according to process parameters. In an HDP-CVD deposition process, for example, a bias power is coupled to the semiconductor wafer to attract ions which sputter (etch) the wafer during deposition (re-sputtering effect), thereby preventing a phenomena known as crowning where the deposition material converges over the trench before an etched feature opening is completely filled with the deposition material. The deposition rate may therefore be more finely tuned to improved CVD deposition properties to, for example, avoid crowning.
The D/S (deposition-sputtering rate ratio) is a commonly used measure of the gap-filling capability of the process. Among the disadvantages of a lower D/S ratio include the possibility of “corner clipping,” or “edge erosion” along the edges of metal lines and the lowering of processing throughput since it requires a relatively longer period of time to achieve the formation of the HDP-CVD oxide. The high density of the plasma can result in significant heating of the wafer during deposition requiring a cooled wafer chuck to cool the wafer during deposition. Generally, higher sputtering rates (lower D/S ratios) tend to increase the temperature of the wafer substrate and as such high temperatures have been necessary at the early stages of gap filling when low deposition/sputter ratios (typically less than 4) are necessary to fill the high aspect ratio channels. Temperatures as high as 400° C. have been observed and at these temperatures significant distortion of the metal features and circuitry have been observed.
On the other hand, a relatively higher D/S ratio results in problems with gap-filling ability leading to the formation of voids. Consequently, many HDP processes according to the prior art to have tended to optimize the HDP-CVD process whereby the D/S ratio is carried out at lower levels in a one step process in order to maximize gap-filling ability.
One type of IMD layer dielectric that has found increasing use is fluorosilicate glass (FSG) also referred to as silicon oxyfluoride. FSG tends to reduce the dielectric constant of IMD layers to levels around 3.5, which in many applications is sufficient to reduce the capacitance of the dielectric layer to desired levels thereby decreasing a signal time constant (RC time constant) which can adversely signal transmission.
One problem with using PSG as a gap filling dielectric layer is that fluorine tends to diffuse through the FSG and attacks the metal lines, for example aluminum, causing a bubble like defect on the aluminum. Although the deposition of barrier layers has been proposed in the prior art, prior art barrier layers have suffered from a lack of presenting a sufficient barrier to fluorine diffusion and achieving sufficient film thickness uniformity, which has tended to result in plasma induced damage at thinner portions of a barrier layer during the HDP-CVD process to deposit the FSG.
There is therefore a need in the semiconductor processing art to develop an improved method for depositing HDP-CVD FSG such that fluorine attack of underlying metallization layers is reduced or avoided and HDP-CVD plasma damage to the wafer process surface is avoided in the HDP-CVD FSG deposition process.
It is therefore an object of the invention to provide develop an improved method for depositing HDP-CVD FSG such that fluorine attack of underlying metallization layers is reduced or avoided and HDP-CVD plasma damage to the wafer process surface is avoided in the HDP-CVD FSG deposition process while overcoming other shortcomings and deficiencies of the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method of reducing plasma induced damage in semiconductor devices and fluorine damage to a metal containing layer.
In a first embodiment, the method includes providing a semiconductor wafer including semiconductor devices including a gate oxide and a process surface including metal lines; carrying out a first high density plasma chemical vapor deposition (HDP-CVD) process to controllably produce a silicon rich oxide (SRO) layer including a relatively increased thickness at a center portion of the process surface compared to a peripheral portion of the process surface; and, carrying out a second HDP-CVD process in-situ to deposit a fluorine doped silicon dioxide layer over the SRO layer to fill a space between the metal lines.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.


REFERENCES:
patent: 6335274 (2002-01-01), Wu et al.
patent: 6380066 (2002-04-01), See et al.
patent: 6528886 (2003-03-01), Liu et al.

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