Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-07
2002-06-11
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S637000, C430S313000, C430S314000, C430S315000, C430S396000
Reexamination Certificate
active
06403431
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a trench in an insulating layer, and more particularly to a method for fabricating a cell capacitor of cylindrical type in the trench.
2. Description of the Related Art
Recent advances in the miniaturization of integrated circuits have led to smaller wafer areas available for devices. High density DRAMs, for example, leave little room for the storage nodes of memory cells. Yet even as the footprint (an area of a silicon wafer allotted for an individual memory cell) shrinks, the storage nodes must maintain a certain minimum charge storage capacity, determined by design and operational parameters to ensure reliable operation of the memory cells. It is thus increasingly important that capacitors achieve a high stored charge storage per unit area of the wafer.
In DRAM cells, charges stored in the capacitor are drained continuously. Therefore, periodic refresh operation is needed to keep charges within the capacitor at a certain level, which can be read. As is well known, frequency of refresh operation is inversely proportional to capacitance of the capacitor. During this refresh operation, read and write operations are impossible. Accordingly, DRAM devices with high capacitance are needed to keep pace with recent trends of high density and high operational speed. Accordingly, several techniques have been recently developed to increase the total charge capacity of the cell capacitor without significantly affecting the wafer area occupied by the cell.
In a capacitor, a dielectric material is deposited between two conductive layers, which form the capacitor plates or electrodes. The amount of charge stored on the capacitor is proportional to the capacitance. C=∈×∈
0
×A/d, where ∈ is the dielectric constant of the capacitor dielectric, ∈
0
is vacuum permittivity, A is the electrode area, and d represents the spacing between electrodes. Some techniques for increasing capacitance include the use of new materials having higher dielectric constants.
Other techniques concentrate on increasing the effective surface area (“A”) of the electrodes by creating folding structures such as stacked capacitors. Such structures better utilize the available chip area by creating three-dimensional shapes to which the conductive plates and capacitor dielectric conform. Such stacked capacitors include, for example double-stacked, fin stacked, cylindrical, spread-stacked, and box-structured capacitors.
Since both the outer and inner surfaces can be utilized as an effective capacitor area, the cylindrical structure is favored over the three-dimensional stacked capacitor, and is more particularly suitable for highly-integrated memory cells.
U.S. Pat. Nos. 5,362,666, 5,728,618, 5,753,547, the disclosures of which are incorporated herein by reference, disclose methods for fabricating a cylindrical capacitor with a single trench etch mask.
Conventionally, cylindrical capacitors are formed by the process of depositing a thick sacrificial oxide layer, etching the sacrificial oxide layer to form trenches by using a single trench etch mask, depositing a storage node material and isolating each cell from one another to form storage nodes. As a DRAM cell scales down to a sub-quarter micron level minimum feature size. It is, however, very difficult to form a photoresist pattern defining the trench regions using current photolithographic processes. Also, the patterned photoresist layer has a round configuration at the corner thereof (so-called “rounding effect”), reducing the dimension of the trenches in the oxide layer (i.e., increasing space between the trenches) and resulting in a reduced surface area of the storage node. Also, the oxide layer may not be sufficiently etched (so-called “not opening phenomenon” of the contact window) and uniformity of the trenches may not be ensured.
Accordingly, there is a need for a method for fabricating trenches in the oxide layer that can allow the formation of trenches exceeding photolithographic resolution limits (i.e., decreasing the space between the trenches) along with uniformity thereof
SUMMARY OF THE INVENTION
The present invention is directed toward providing a method of forming a trench in an insulating layer that can exceed the photolithographic resolution limits and can provide a uniformity of the trench, and more particularly directed toward providing a method for fabricating a cylindrical capacitor in the trench.
A feature of the present invention is the formation of a trench-etching mask exceeding the photolithographic resolution limits. The trench-etching mask can be formed using a two-step photolithographic process. First line patterns are formed on the sacrificial oxide layer. The first line patterns are parallel and spaced apart from one another. The gap or space dimension between adjacent patterns corresponds to the dimension of the storage node measured at the longer direction thereof. Then, second line patterns are formed on the first line patterns and on the sacrificial oxide layer, intersecting the first patterns and defining a trench etching mask. The second line patterns are also parallel and spaced apart from one another. The gap or space dimension between adjacent patterns corresponds to the dimension of the storage node measured at the shorter direction thereof. Namely, the intersecting first and second patterns define rectangular configuration trench areas, which define a rectangular storage node configuration. Using this pattern, the underlying sacrificial oxide layer is etched to form trenches with good etching profile while avoiding not opening and rounding phenomena.
Furthermore, in order to increase trench areas, the resulting trench etching mask is then etched partially to form a trench-etching mask that exceeds photolithographic resolution limits. The etching of the trench-etching mask can be carried out by wet etching using a wet chemical. Also, etching of the trench etching mask can be carried out by the process of forming an oxide layer by dry oxidation on the trench etching mask and then etching the resulting oxide layer.
Briefly, in accordance with the present invention, there is provided a method of forming a trench in a sacrificial oxide layer in semiconductor manufacturing. The method comprises depositing an insulating layer on a semiconductor topology. A first plurality of spaced-apart and parallel patterns are formed on the insulating layer. The first patterns are made of a material that has an etching selectivity with respect to the insulating layer. For example, polysilicon, nitride and alumina can be used. A second plurality of spaced-apart and parallel patterns are formed on the insulating layer and on the first patterns so as to intersect the first patterns. The second patterns are made of a material that has an etching selectivity with respect to the insulating layer. For example, polysilicon, nitride, and alumina can be used. The intersecting first and second patterns define a trench mask pattern. Using the trench mask pattern, the underlying insulating layer is etched to form a plurality of trenches to the semiconductor topology.
According to an aspect of the above-mentioned method, the trench-etching mask can be partially etched to enlarge the trench areas defined by the trench-etching mask. Enlarging the trenches can be carried out by wet etching using a wet chemical. Alternatively, enlarging the trench is carried out by the process of oxidizing the trench mask and then etching the resulting oxide layer. Accordingly, a finer pattern, than can be printed by the photolithographic resolution is obtained. Also, with a relaxed design rule, desired pattern size can be obtained and increased semiconductor circuit density.
In accordance with the present invention, there is provided a method of forming a trench in an insulating layer in a semiconductor manufacturing. The method comprises forming an insulating layer on a semiconductor topology. The semiconductor topology includes a semico
Chung Tae-Young
Uh Hyung-Soo
Marger & Johnson & McCollom, P.C.
Niebling John F.
Pompey Ron
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