Method of forming high voltage junction in semiconductor device

Details Method of forming high voltage junction in semiconductor device Method of forming high voltage junction in semiconductor device

2005-04-12

2005-04-12

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06878596

ABSTRACT:
The present invention relates to a method of forming a high voltage junction in a semiconductor device. The method includes forming a double diffused drain junction, and making amorphous the double diffused drain junction to a first depth by implanting an impurity having a high atomic weight than an impurity injected into the double diffused drain junction, implanting an impurity so that the concentration of the concentration of an impurity to a second depth lower than the first depth and then activating the impurities. Thus, the present invention can reduce the sheet resistance by prohibiting diffusion of an impurity, prohibit a channeling phenomenon by lowering the depth of the junction, and remove crystal defects by sufficiently activating an impurity and since a subsequent annealing process for activation can be performed at a high temperature, and thus improve reliability of a process and an electrical characteristic of the device.

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