Method of forming high K tantalum pentoxide Ta2O5 instead of...

Details Method of forming high K tantalum pentoxide Ta2O5 instead of... Method of forming high K tantalum pentoxide Ta2O5 instead of...

1999-03-05

2001-10-30

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S785000

Reexamination Certificate

active

06309927

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to flash memory devices such as EEPROMs. More particularly, the present invention relates to flash memory devices exhibiting a number of desirable characteristics including one or more of less charge trapping, less charge leakage and increased tunnel oxide reliability.
BACKGROUND ART
Nonvolatile memory devices include flash EEPROMs (electrical erasable programmable read only memory devices).
FIG. 1
represents the relevant portion of a typical flash memory cell
10
. The memory cell
10
typically includes a source region
12
, a drain region
14
and a channel region
16
in a substrate
18
; and a stacked gate structure
20
overlying the channel region
16
. The stacked gate
20
includes a thin gate dielectric layer
22
(commonly referred to as the tunnel oxide) formed on the surface of the substrate
18
. The stacked gate
20
also includes a polysilicon floating gate
24
which overlies the tunnel oxide
22
and an interpoly dielectric layer
26
which overlies the floating gate
24
. The interpoly dielectric layer
26
is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers
26
a
and
26
b
sandwiching a nitride layer
26
c
. Lastly, a polysilicon control gate
28
overlies the interpoly dielectric layer
26
. The channel region
16
of the memory cell
10
conducts current between the source region
12
and the drain region
14
in accordance with an electric field developed in the channel region
16
by the stacked gate structure
20
.
The ONO interpoly dielectric layer has a number of important functions including insulating the control gate from the floating gate. However, high temperature processes such as a wet oxidation process and long processing times are associated with the fabrication of an ONO interpoly dielectric layer. High temperatures such as 950° C. and above are undesirable because they tend to degrade polysilicon and/or tunnel oxide deleteriously increasing charge trapping. Specifically associated with forming the top oxide layer of an ONO interpoly dielectric layer using a wet oxidation process, an undesirably large amount of the nitride film may be consumed. Consequently, the resultant nitride layer is thinned which can cause charge leakage from the floating gate to the control gate. Another problem with forming the top oxide layer using a wet oxidation process is that it sometimes leads to junction problems at the nitride layer—top oxide layer interface. Long processing times makes the ONO interpoly dielectric layer fabrication process inefficient.
Even after an ONO interpoly dielectric layer is formed, there are a number of concerns. For example, if the top oxide layer is too thick, the required programming voltage increases undesirably. On the other hand, if the top oxide layer is too thin (for example, less than 10 Å), charge retention time decreases undesirably since the charge tends to leak. If the nitride layer is too thin, charge leakage from the floating gate to the control gate may be caused, further decreasing charge retention time. Precisely controlling the thicknesses of the oxide layers and the nitride layer is a notable concern. Furthermore, it is difficult to provide three successive layers having uniform and even thickness on a consistent basis.
Using alternative dielectric layers in place of conventional ONO interpoly dielectric layers is known, such as tantalum oxide based interpoly dielectric layer, but these layers do not possess or exhibit the characteristics required of high quality interpoly dielectric layers in flash memory cells.
In view of the aforementioned concerns and problems, there is a need for flash memory cells of improved quality, particularly interpoly dielectric layers having improved quality, and more efficient methods of making such memory cells.
SUMMARY OF THE INVENTION
As a result of the present invention, a flash memory cell having improved reliability is obtainable by providing an improved interpoly dielectric layer. By forming a bilayer interpoly dielectric according to the present invention, an interpoly dielectric having a low defect density, high coupling ratio, high dielectric constant, better time dependent dielectric breakdown and less interface traps is obtainable wherein charge leakage from the floating gate to the control gate is prevented while Fowler-Nordheim electron tunneling is facilitated. Moreover, forming a bilayer intelpoly dielectric in accordance with the present invention does not degrade or deleteriously effect the polysilicon layers and the tunnel oxide layer. The present invention also makes it possible to precisely control the thickness of the interpoly dielectric layer. Another advantage associated with the present invention is that the two layers of the bilayer interpoly dielectric are very compatible thereby minimizing junction problems therebetween.
In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising an oxide layer over the first polysilicon layer, and a tantalum pentoxide layer over the oxide layer, wherein the tantalum pentoxide layer is made by chemical vapor deposition at a temperature from about 200° C. to about 650° C. using an organic tantalum compound and an oxygen compound, and heating in an N
2
O atmosphere at a temperature from about 700° C. to about 875° C.; forming a second polysilicon layer over the insulating layer; etching at least the first polysilicon layer, the second polysilicon layer and the insulating layer, thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.
In another embodiment, the present invention relates to a method of forming an insulating layer for a flash memory cell, involving the steps of depositing an oxide layer having a thickness from about 30 Å to about 70 Å; and depositing a tantalum pentoxide layer over the oxide layer, wherein the tantalum pentoxide layer is deposited by chemical vapor deposition using an organic tantalum compound, an oxygen compound and a carrier gas, and heating in an N
2
O atmosphere at a temperature from about 700° C. to about 875 ° C. for a time from about 40 seconds to about 80 seconds.
In yet another embodiment, the present invention relates to a method of forming a high K interpoly dielectric layer between a floating gate and a control gate in a flash memory cell comprising a substrate, a tunnel oxide over the substrate, the floating gate over the tunnel oxide, the high K interpoly dielectric layer over the floating gate, and the control gate over the high K interpoly dielectric layer, wherein the high K interpoly dielectric layer comprises an oxide layer over the floating gate, and a tantalum pentoxide layer over the oxide layer, involving the steps of forming an oxide layer having a thickness from about 30 Å to about 70 Å at a temperature below about 900° C.; and forming a tantalum pentoxide layer over the oxide layer, wherein the tantalum pentoxide layer is deposited by chemical vapor deposition using an organic tantalum compound, an oxygen compound and a carrier gas at a temperature below about 700° C., and heating in an N
2
O atmosphere at a temperature below about 900° C., wherein the high K interpoly dielectric layer has a dielectric constant of at least about 20.


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