Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-03-11
1999-12-07
Monin, Jr., Donald L.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438257, H01L 218247
Patent
active
059982640
ABSTRACT:
The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers is formed on the side walls of the gate structure. Then, source/drain structure of the device is fabricated. Next, the side wall spacers is removed to expose a portion of the source and drain. Then, an undoped amorphous silicon layer is formed on the surface of the gate structure, the oxide layer and the exposed source and drain. A dry oxidation process is used to convert the amorphous silicon layer into textured tunnel oxide at the interface of the substrate and the oxide. A polysilicon layer is than formed, followed by chemical mechanical polishing the layer. A conductive layer is formed on the polysilicon layers. Subsequently, a silicon nitride layer deposited by jet vapor deposition (JVD) is formed on the conductive layer. A high k dielectric layer is next formed on the JVD nitride. A conductive layer to serve as control gate is subsequently formed on the high k dielectric layer. A patterning technique is used to pattern the layers.
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Monin, Jr. Donald L.
Pham Hoai V.
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