Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1998-07-14
2000-12-19
Quach, T. N.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438653, 438656, 438680, H01L 213205
Patent
active
061627151
ABSTRACT:
A gate electrode connection structure formed by deposition of a tungsten nitride barrier layer and a tungsten plug, where the tungsten nitride and tungsten deposition are accomplished in situ in the same chemical vapor deposition (CVD) chamber. The tungsten nitride deposition is performed by plasma enhanced chemical vapor deposition (PECVD) using a plasma containing hydrogen, nitrogen and tungsten hexafluoride. Before deposition the wafer is pretreated with a hydrogen plasma to improve adhesion. The tungsten deposition process may be done by CVD using tungsten hexafluoride and hydrogen. A tungsten nucleation step is included in which a process gas including a tungsten hexafluoride, diborane and hydrogen are flowed into a deposition zone of a substrate processing chamber. Following the nucleation step, the diborane is shut off while the pressure level and other process parameters are maintained at conditions suitable for bulk deposition of tungsten.
REFERENCES:
patent: 4436761 (1984-03-01), Hayashi et al.
patent: 4713259 (1987-12-01), Gartner et al.
patent: 4745031 (1988-05-01), Nakayama et al.
patent: 4766006 (1988-08-01), Gaczi
patent: 4894256 (1990-01-01), Gartner et al.
patent: 4913929 (1990-04-01), Moslehi et al.
patent: 4965090 (1990-10-01), Gartner et al.
patent: 5011705 (1991-04-01), Tanaka
patent: 5132756 (1992-07-01), Matsuda
patent: 5135775 (1992-08-01), Foller et al.
patent: 5232872 (1993-08-01), Ohba
patent: 5283085 (1994-02-01), Gartner et al.
patent: 5306666 (1994-04-01), Izumi
patent: 5487923 (1996-01-01), Min et al.
patent: 5576071 (1996-11-01), Sandhu
patent: 5670808 (1997-09-01), Nishhori et al.
patent: 5710070 (1998-01-01), Chan
patent: 5716870 (1998-02-01), Foster et al.
patent: 5719410 (1998-02-01), Suehiro et al.
patent: 5733816 (1998-03-01), Iyer et al.
patent: 5744398 (1998-04-01), Wanlass
patent: 5780908 (1998-07-01), Sekiguchi et al.
patent: 5786256 (1998-07-01), Gardner et al.
patent: 5913145 (1999-06-01), Lu et al.
patent: 5925918 (1999-07-01), Wu et al.
patent: 5962904 (1999-10-01), Hu
patent: 6015727 (2000-01-01), Wanlass
Nakajima, T., et al., Preparation of Tungsten Nitride Film by CVD Method Using WF.sub.6, J. Electrochemical Society: Solid-State Science and Technology, pp.3175-3178, Dec. 1987, 134(12).
Kim, Y. T., et al, "New Method to Supress encroachment by Plasma-Deposited Beta-Phase Tungsten Nitride Thin Films", Appl. Phys. Lett., vol.59, No.8, pp. 929-931, Aug. 1991.
Marcus, S. D. et a., "Characterization of Low Pressure Chemically Vapor-Deposited Tungsten Nitride Films", Thin Solid Films, pp.330-333, 1993.
Oku, T., et al. "Thermal Stability of WN.sub.x and TaN.sub.x Diffusion Barriers Between Si and Cu", VMIC Conference, Jun. 27-29, 1995, pp. 182-185.
Akasaka, Y. et al., "Low-Resistivity Poly-Metal Gate Electrode Durable for High-Temperature Processing", VMIC Conf. Jun. 27-29, 1995, pp. 168-179.
Park, B.L., et al., "A Novel Deep-Submicron Contact Technology Using the PECVD-Grown WN.sub.x Barrier Layer", VMIC Conferenvce Jun. 27-29, 1995, pp. 186-192.
Ghanayem Steve G.
Jian Ping
Lai Kevin
Leung Cissy
Mak Alfred
Applied Materials Inc.
Quach T. N.
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